日本語
College of Science and Engineering  /
Department of Electronic and Computer Engineering

 (Male)
 Katsuhiro   YAMAZAKI  Professor

■Concurrent affiliation
Research Organization of Science and Technology   /
VLSI Center
Graduate School of Science and Engineering
■Graduate school/University/other
03/1978  Kyoto University  "Graduate School, Division of Engineering"  Information Science  Doctoral course first term (Master's)  Completed
 Kyoto University  Graduated
■Academic degrees
Doctor of Engineering (02/1986 Kyoto University)  
■Career history
09/1980-03/1988  Assistant Professor, Dept.of Computer Science, Utsunomiya University
04/1988-03/1994  Associate Professor, Dept. of Computer Science, Ritsumeikan University
09/01/1992-08/31/1993  Honorary Visiting Research Fellow, Centre for Novel Computing, University of Manchester
04/1994-03/2004  Professor, Dept. of Computer Science, Ritsumeikan University
04/2004-03/2012  Professor, Dept. of VLSI Design, Ritsumeikan University
04/2012-  Professor, Dept. of Electronic and Computer Engineering, Ritsumeikan University
■Committee history
1997-1999  Information Processing Society of Japan  Kansai Section Secretary
1999-2011  Information Processing Society of Japan  Kansai Section Councilor
2003-2008  Information Processing Society of Japan  Kansai Section VLSI System Society Councilor
2008-2014  Information Processing Society of Japan  Kansai Section MAnufacturing Platform Society Councilor
 Information Processing Society of Japan  Transactions Referee
2005-2009  Information Processing Society of Japan  Transactions Committee Member
2005-2011  Institute of Electronics, Information and Communication Engineers  Computer System Research Comittee Member
2007-2011  IEEE  Kansai Section SAC Member
04/2006-03/2011  IEEE  Ritsumeikan Student Branch Counselor
05/2012-05/2014  Institute of Electronics, Information and Communication Engineers  Kansai Section Secretary
05/2012-05/2015  Informtion Processing Society of Japan  Kansai Section Member
09/2014-03/2015  Institute of Electronics, Information and Communication Engineers  2015 IEICE General Conference Executive Committee Chairperson
09/2014-09/2015  Institute of Electronics, Information and Communication Engineers  IEICE General Conference Steering Committee Member
■Academic society memberships
Information Processing Society of Japan  
Institute of Electronics, Information and Communication Engineers  
ACM  
IEEE  
Seiwa Scholars Society  
■Licenses and qualifications
EIKEN Grade Pre-1  (1987)   
■Subject of research
Parallel Computing
Heterogeneous Computing
■Research summary
Parallel Computing, Heterogeneous Computing, Hardware Software Co-design

 (1) Multi-ALU Processors on FPGAs
We have been studying Multi-ALU Processor (MAP) s on FPGAs. MAP has two, four, and eight ALUs, thus both parallel operations and chaining operations are available.
The objectives of this project are not only to design, implement, and actually run the processor on FPGAs, but also to investigate the possibilities of operation level parallelism. Students can acquire processor designing capabilities and FPGA utilization techniques by designing MAP on FPGAs with Verilog HDL. Thus they can acquire a wide knowledge of hardware and software, because MAP actually runs on FPGAs using a debugger, a monitor and a simulator.

(2) Heterogeneous Computing
GPUs and FPGAs have improved very rapidly, and it is very important to acquire parallelization mechanisms and fully utilize these devices for a wide range of applications. We have implemented real-time raytracing on GPUs. Currently, we are developing a recognition system of oracular bone inscriptions by template matching on GPUs. We are also interested in pipelining BLOB detections. Dual and quad pipelining systems of BLOB detections have been implemented on FPGAs, and currently we are trying to apply these systems to front vehicle detection.
■Research keywords
parallel computing, hardware software co-learning, hardware software optimum division, hardware synthesis, reconfigurable computing, hybrid parallel processing, GPU computing, real-time ray tracing, FPGA, multi-core, OpenMP, MPI, multi-pipelining, oracular bone inscriptions recognition, Igo system 
■Research activities   (Even top three results are displayed. In View details, all results for public presentation are displayed.)

Books
Parallel Programming using Similar Cases -from LU Decomposition to Napsack Problems-  Yamazaki and Ando  bit  30,7,pp.23-30  07/1998
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Papers
Recognition of Oracular Bone Inscriptions Using Template Matching  Lin Meng, Y. Fujikawa, A. Ochiai, T. Izumi and K. Yamazaki  Int. J. of Computer Theory and Engineering (IJCTE)  8/ 1, 53-57  02/2016
BLOB Detection by Dual Pipelines and its Application to Front Vehicle Detection on FPGAs  Nojiri, Mou, Yamazaki  FIT2015, 14th Forum on Information Tecnology, RC-002  27-34  09/2015
Recognition of Oracular Bone Inscriptions Using Template Matching  Lin Meng, Y. Fujikawa, A. Ochiai, T.Izumi and K.Yamazaki  2nd International Conference on Information and Computer Technology(ICICT2014)  C010  08/2014
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Research presentations
Characteristics Detection from Original Images of Oracle Bone Inscriptions and Searching Similar Templates  FIT2015, H-014  09/07/2016
Design of Parallel and Chained Operation Units for Four ALU Processors on FPGAs  IPSJ 78th Annual Convention, 6G-05  03/12/2016
BLOB Detection using quad pipelines on FPGAs  IPSJ 78th Annual Convention  03/10/2016
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Grants-in-Aid for Scientific Research (KAKENHI)
Link to Grants-in-Aid for Scientific Research -KAKENHI-

Achievements of joint / funded research
Research Development of Digital TDI Camera Systems and its Implementation  05/2010-02/2011  Joint research
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Academic awards
Nikkei BP  8th LSI IP Design Award, Development Incentive award, NikkeiBP  2006
Information Processing Society of Japan  Yamauchi Achievement Award  1994
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Research exchange preferred theme
Large scale parallel processing using PC clusters and GPUs  Solves large scale problems in high speed using PC clusters and GPUs.  Joint research
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■Teaching experience   (Even top three results are displayed. In View details, all results for public presentation are displayed.)

Courses taught
2017  Electronic and Computer Engineering Laboratory 3  Laboratory work / Practical experience / Skills practice
2017  Thesis  Seminar
2017  Applied Exercises for Electronic and Computer Eng.  Seminar
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Teaching achievements
電気通信大学 吉永研究室との学生交流を行なった。  09/2017-09/2017
北陸先端大学院大学 井口研究室との学生交流を行なった。  09/2016-09/2016
東北大学 佐野研究室との学生交流を行なった。  03/2016-03/2016
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■Message from researcher
高性能コンピューティング、ハード・ソフトコデザイン、事例ベース推論
 「高性能計算達成の手段として、プロセッサを複数台用いる並列処理は最も重要なテーマの一つです」と語る山崎先生の専門は計算機科学。
現在、得丸・渡部両教授と共同で、高並列マシンの神経回路網、図形処理などへの応用とそのためのアーキテクチャを研究中です。研究のもう一つの柱は事例ベース推論。「専門家が問題を解決する時、ルール以外に豊富な経験が物を言います。これをソフトウェアで実現するわけです」と説明。過去の類似した並列プログラムの構造を再利用して、並列プログラミングを容易にするシステムを試作しました。
現在、PC16台を高速ネットワークで接続してPCクラスタを構築し、その上での並列プログラミングの研究が進展中です。

'76年京大工学部情報工学科を卒業。大学院で萩原宏教授の下で並列処理を研究、宇都宮大を経て、'88年本学へ。『低レベル並列計算機におけるマイクロプログラムの記述とその処理』が学位論文。旅行、囲碁が趣味。工博。(談)
■URL
 High Performance Computing Laboratory.
■Research keywords(on a multiple-choice system)
Computer system
Hardware Software Co-design
Software
High performance computing Parallel Computing
Heterogeneous Computing
Learning support system