論文
公開件数:54件
No. 発表論文の標題 著者名等 掲載誌名 巻/号,頁 出版年月 ISSN DOI URL
1 Logical Qubit Layout Problem for ICM Representation
Nurul Ain Binti Adnan, Shigeru Yamashita
Journal of Information Processing
26/ (2018), 20-28
2018/01
1882-6652


2 Stochastic Number Generation with the Minimum Inputs
Ritsuko Muguruma, Shigeru Yamashita
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Vol. E100.A/ 8, 1661-1671
2017/08



3 A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers
Takahiro Yamamoto Ittetsu Taniguchi Hiroyuki Tomiyama Shigeru Yamashita Yuko Hara-Azumi
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Volume E100/ 7, 1496-1499
2017/07



4 Reduction of Quantum Cost by Making Temporary Changes to the Function
Nurul Ain Binti Adnan, Shigeru Yamashita, Alan Mischenko
IEICE Transactions on Information and Systems
Vol. E100.D/ 7, 1393-1402
2017/07



5 A Full-Flexibility-Guaranteed Pin-Count Reduction Design for General-Purpose Digital Microfluidic Biochips
Trung Anh DINH Shigeru YAMASHITA Tsung-Yi HO
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
E99-A/ 2, 570-578
2016/02



6 An Energy-Efficient Patchable Accelerator and Its Design Methods
Hiroaki YOSHIDA, Masayuki WAKIZAKA, Shigeru YAMASHITA and Masahiro FUJITA
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
E97-A/ 12, 2507-2517
2014/12



7 ビットごとの排他的論理和を利用した画像の新しい類似度指標の提案とその動き検出プロセッサへの適用と評価
崔 英鮮, 山下 茂
電子情報通信学会英文論文誌A
J97-A/ 3
2014/03



8 Clique-Based Architectural Synthesis of Flow-Based Microfluidic Biochips
Trung Anh DINH Shigeru YAMASHITA Tsung-Yi HO, Yuko HARA-AZUMI
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
E96-A/ 12, 2668-2679
2013/12



9 Selective Check of Data-Path for Effective Fault Tolerance
Tanvir Ahmed, Jun Yao, Yuko Hara-Azumi, Shigeru Yamashita, Yasuhiko Nakashima
IEICE Transactions on Information and Systems (Special Section on "Reconfigurable Systems"), vol.E96-D, no.8, pp.1592-1601, Aug. 2013.
E96-D/ 8, 1592-1601
2013/08



10 Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication
M. Villagra, M. Nakanishi, S. Yamashita, Y. Nakashima
IEICE Transactions on Information and Systems
E96-D/ 1, 1-8
2013/01



11 Quantum walks on the line with phase parameters
M. Villagra, M. Nakanishi, S. Yamashita, Y. Nakashima
IEICE Transactions on Information and Systems
E95-D/ 3, 722-730
2012/03



12 Synthesis of Semi-Classical Quantum Circuits
Shigeru Yamashita, Shin-ichi Minato, D. Michael Miller
Journal of Multiple-Valued Logic and Soft Computing
18/ 1, 99-114
2012/01



13 An Efficient Framework to Utilize Grover Search
Shigeru Yamashita, Masaki Nakanishi
Journal of Nanjing University of Posts and Telecommunications,
31/ 2, 85-94
2011/04



14 An efficient conversion of quantum circuits to a linear nearest neighbor architecture
Yuichi Hirata, Masaki Nakanishi, Shigeru Yamashita and Yasuhiko Nakashima
Quantum Information and Computation
11/ 1, 142-166
2011/01



15 量子探索アルゴリズムとその利用
山下茂
電子情報通信学会会誌
93/ 9, 785-791
2010/09



16 Fast equivalence-checking for quantum circuit
S. Yamashita, I. L. Markov
Quantum Information and Computation
10/ 9&10, 721-734
2010/09



17 量子計算の並列シミュレーションにおける通信量削減手法
柴田章博, 中田尚, 中西正樹, 山下茂, 中島康彦
電子情報通信学会論文誌 D
J93-D/ 3, 253-264
2010/03



18 Synthesis of quantum circuits for d-level systems by using Cosine-Sine decomposition
Y. Makajima, Y. Kawano, H. Sekigawa, M. Nakanishi, S. Yamashita, Y. Nakashima
Quantum Information and Computation
9/ 5&6, 423-443
2009



19 Multi-Party Quantum Communication Complexity with Routed Messages
S. Tani, M. Nakanishi, S. Yamashita
IEICE transactions on Information and Systems
E92-D/ 2, 191-199
2009/02



20 DDMF: An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical Restriction
S. Yamashita, S. Minato, D. M. Miller
IEICE Trans. Fundamentals
E91-A/ 12, 3793-3802
2008/12



21 Robust quantum algorithms computing OR with e-biased oracles
T. Suzuki, S. Yamashita, M. Nakanishi, K. Watanabe
IEICE transactions on Information and Systems
E90-D/ 2, 395-402
2007



22 Improved Algorithms for Quantum Identification of Boolean Oracles
A. Ambainis, K. Iwama, A. Kawachi, R. Raymond, S. Yamashita
Theoretical Computer Science (Elsevier Science)
378/ 1, 41-53
2007



23 Quantum Lower Bounds for the Goldreich-Levin Problem
Mark Adcock, Richard Cleve, Kazuo Iwama, Raymond Putra, Shigeru Yamashita
Information Processing Letters
97/ 5, 208-211
2006



24 Query Complexity of Quantum Biased Oracles (Invited Paper)
K. Iwama, Rudy Raymond, S. Yamashita
In: H. Imai and M. Hayashi (Eds.) Quantum Computation and Information: From Theory to Experiment, Springer-Verlag
19-42
2006



25 Quantum Identification of Boolean Oracles (Invited Paper)
A. Ambainis, K. Iwama, A. Kawachi, Rudy Raymond, S. Yamashita
In: H. Imai and M. Hayashi (Eds.) Quantum Computation and Information: From Theory to Experiment, Springer-Verlag
3-18
2006



26 (4,1)-Quantum random access coding does not exist―one qubit is not enough to recover one of four bits
M. Hayashi, K. Iwama, H. Nishimura, R. Raymond, S. Yamashita
New Journal of Physics
8/ 129
2006



27 An efficient and effective algorithm for online task placement with I/O communications in partially reconfigurable FPGAs
M. Tomono, M. Nakanishi, S. Yamashita, K. Nakajima, and K. Watanabe
IEICE Trans. Fundamentals
E89-A/ 12, 3416-3426
2006/12



28 Quantum Sampling for Balanced Allocations
K. Iwama, A. Kawachi, S. Yamashita
IEICE transactions on Information and Systems
E88-D/ 1, 39-46
2005



29 能動関数によるアサーション検証設計
渡邉勝正, 井上晶広, 伴野充, 蔵川圭, 中西正樹, 山下 茂
コンピュータソフトウェア
22/ 3, 76-91
2005



30 Quantum versus Classical Pushdown Automata in Exact Computation
Y. Murakami, M. Nakanishi, S. Yamashita, K. Watanabe
Journal of IPSJ
46/ 10, 2471-2480
2005



31 Quantum Biased Oracles
K. Iwama, A. Kawachi, S. Yamashita
Journal of IPSJ
46/ 10, 2400-2408
2005



32 General Bounds for Quantum Biased Oracles,
K. Iwama, R. Raymond, S. Yamashita
Journal of IPSJ
46/ 10, 2481-2491
2005



33 Explicit implementation of quantum circuits on a quantum-dot-cellular-automata-like architecture
Y. Kawano, S. Yamashita, and M. Kitagawa
Physical Review A
72/ 1, 012301
2005/07



34 SPFD-Based Flexible Transformation of LUT-Based FPGA Circuits
K. Tanaka, S. Yamashita, Yahiko Kambayashi
IEICE Trans. Fundamentals
E88-A/ 4, 1039-1046
2005/04



35 変換理論による量子回路設計 (招待論文)
山下茂
数理科学, サイエンス社
492, 50-58
2004/06



36 Transformation Rules for CNOT-based Quantum Circuits and Their Applications (Invited Paper)
K. Iwama, S. Yamashita
New Generation Computing
21/ 4, 297-317
2003



37 Efficient Algorithms for NMR Quantum Computers with Small Qubits
N. Kunihiro, S. Yamashita
New Generation Computing
21/ 4, 329-337
2003



38 Quantum Query Complexity of Biased Oracles
K. Iwama, R. Raymond H. P., S. Yamashita
Information Technology Letters
17-18
2003/09



39 Summary: A New Notion for Functional Flexibility (Invited Paper)
S. Yamashita, H. Sawada, A. Nagoya
the IEEE CAS Magazine
2/ 2, 52-64
2002



40 量子アルゴリズムの設計理論構築に向けて (招待論文)
山下茂
NTT R&D
51/ 10, 784-790
2002/10



41 量子コンピュータ科学入門 (招待論文)
岩間一雄, 山下茂
電子情報通信学会誌
85/ 8, 618-625
2002/08



42 A Complete Set of Transformation Rules for Quantum Boolean Circuits with CNOT gates
K. Iwama, S. Yamashita
Superlattices and Microstructures
31/ 2-4, 181-192
2002/02



43 A General Framework to Use Various Decomposition Methods for LUT Network Synthesis
S. Yamashita, H. Sawada, A. Nagoya
IEICE Trans. Fundamentals
E84-A/ 11, 2915-2922
2001/11



44 (博士取得論文)Studies on Logic Synthesis Methods for Look-Up Table based FPGAs



2001/07



45 Efficient Kernel Generation based on Implicit Cube Set Representations and Its Applications
H. Sawada, S. Yamashita, A. Nagoya
IEICE Trans. Fundamentals
E83-A/ 12, 2513-2519
2000/12



46 PCA可変部向けの論理最適化手法 (招待論文)
名古屋彰, 山下茂, 稲森稔, 澤田宏
NTT R&D
49/ 9, 537-545
2000/09



47 SPFD: A New Method to Express Functional Flexibility
S. Yamashita, H. Sawada, A. Nagoya
IEEE Trans. CAD
19/ 8, 840-849
2000/08



48 SPFD: 論理関数の自由度の新しい表現方法
山下茂, 澤田宏, 名古屋彰
電子情報通信学会論文誌A
J82-A/ 7, 1047-1056
1999/07



49 An Efficient Method for Finding an Optimal Bi-Decomposition
S. Yamashita, H. Sawada, A. Nagoya
IEICE Trans. Fundamentals
E81-A/ 12, 2529-2537
1998/12



50 Reduction of the Number of FPGA Blocks by Maximizing Flexibility of Internal Functions
T. Kouda, S. Yamashita, Y. Kambayashi
IEICE Trans. Fundamentals
E81-A/ 12, 2554-2562
1998/12



51 Restructuring Logic Representations with Simple Disjunctive Decompositions
H. Sawada, S. Yamashita, A. Nagoya
IEICE Trans. Fundamentals
E81-A/ 12, 2538-2544
1998/12



52 Optimization Methods for Lookup-Table- Based FPGAs Using Transduction Method (Invited Paper)
S. Yamashita, Y. Kambayashi, S. Muroga
Systems and Computers in Japan, John Wiley & Sons, Inc.
27/ 12, 92-101
1996/11



53 トランスダクション法によるWired-Logicを併用した論理回路の最適化
山下茂, 上林彌彦, 室賀三郎
電子情報通信学会論文誌D-I
J79-D-1/ 3, 132-139
1996/03



54 許容関数に基づいた表参照型FPGAの最適化手法
山下茂, 上林彌彦, 室賀三郎
電子情報通信学会論文誌D-I
J78-D-I/ 11, 878-885
1995/11