Researcher Database

（Last updated : 2021-12-14 12:22:51）

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IZUMI Tomonori

Department / Course College of Science and Engineering Department of Electronic and Computer Engineering

Title / Position Professor

Other Affiliations
1.	Graduate School of Science and Engineering
2.	Kinugasa Research Organization Institute of Disaster Mitigation for Urban Cultural Heritage
3.	Research Organization of Science and Technology VLSI Center

Academic background
1.	～1998/03	Doctoral Program (2nd Semester) │ Department of Electrical and Electronic Engineering │ Graduate School, Division of Science and Engineering │ Tokyo Institute of Technology │ Completed Ph.D (Electrical and Electronic Engineering)
2.	～1992/03	Department of Computer Engineering │ Faculty of Engineering │ Tokyo Institute of Technology │ Graduated
3.	～1994/03	Doctoral Program (1st Semester) │ Department of Electrical and Electronic Engineering │ Graduate School, Division of Science and Engineering │ Tokyo Institute of Technology │ Completed

Business career
1.	1998/04/01 ～ 2005/03/31	Research Associate │ Graduate School of Informatics │ Kyoto University
2.	2005/04/01 ～ 2007/03/31	Associate Professor │ College of Science and Engineering │ Ritsumeikan University
3.	2007/04/01 ～ 2015/03/31	Associate Professor │ College of Science and Engineering │ Ritsumeikan University
4.	1998/07/01 ～ 2017/06/30	Senior Research Scientist │ │ Synthesis Corporation
5.	2001/04/01 ～ 2001/09/30	Lecturer │ Academy of System LSI Technology │ Synthesis Corporation
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Committee and society
1.	2010 ～ 2020	HEART (International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies) 2010-2020 Program Committee Member, 2012 Design Contest Chair
2.	2000 ～ 2019	SASIMI (Synthesis And System Integration of Mixed Information Technologies) 2000, 2001 Secretary, 2003, 2004, 2016, 2018, 2019 Program Committee Member, 2006, 2007 TPC Secretary, 2012 Local Arrangement Chair, 2013, 2016 Finance Chair
3.	2007 ～ 2019	The Institute of Electronics, Information and Communication Engineers (IEICE)
4.	2013 ～ 2018	ICFPT(International Conference on Field-Programmable Technology) 2013 Local Arrangement Chair, 2018 Registration Chair
5.	2018 ～ 2018	ATAIT (International Symposium on Advanced Technologies and Applications in the Internet of Things) Steering Committee member
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Research activities
1.		The Institute of Electronics, Information and Communication Engineers
2.		Information Processing Society of Japan
3.		Institute of Electrical and Electronic Engineers
4.		the Institute of Image Information and Television Engineers
5.		the Institute of Systems, Control and Information Engineers
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Subject of research
1.	Arcitectures, Design Methodologies and Applications of Dynamic Reconfigurable Systems

Research summary
Arcitectures, Design Methodologies and Applications of Dynamic Reconfigurable Systems In developing information equipment that increasingly requires high and multi-feature and higher performance in the recent years, it has become more important to take the system configuration (system architecture) that effectively combines built-in processors with special-purpose circuits. Moreover, greater attention has been given to the hardware that can change (reconfigure) features in order to meet rapidly changing image and speech coding standards or communication standards or to effectively utilize the limited calculation resources in various processing. Therefore, we conduct research and development on configuration of the information processing system (architecture, devices) comprised of built-in processors, hardware engine and reconfigurable hardware, design and application. As a concept never seen before, we conduct research and development on, among others, "self-recongirable" hardware system in which hardware can rewrite itself depending on the circumstances.

Present specialized field
Computer system (Keyword：LSI, Reconfigurable Systems, Design Methodology, Architecture, Algorithm)

Books
1.	2018/09	Principles and Structures of FPGAs │ ,pp.87-115 (Co-authored)

Papers
1.	2021/03	A Demodulation Method Using a Gaussian Mixture Model For Unsynchronous Optical Camera Communication with On-off Keying │ Journal of Lightwave Technology │ 39,pp.1742-1755 (Co-authored)
2.	2019/03	Example-based Face-image Restration for Block-noise Reduction │ Journal of Image and Graphics │ 7 (1),pp.9-17 (Co-authored)
3.	2018/12	Face Image Super-Resolution with Adaptive Patch Size to Scaling Factor │ Journal of Image and Graphics │ 6 (2),pp.167-173 (Co-authored)
4.	2017/11	Example-based Face Image Super-resolution Taking into Consideration Correspondence of Facial Parts │ Trans. on Electrical and Electronic Engineering (TEEE-C) │ 12 (6),pp.917-924 (Co-authored)
5.	2016/02	Recognition of Oracular Bone Inscriptions Using Template Matching │ Int. J. of Computer Theory and Engineering │ 8 (1),pp.53-57 (Co-authored)
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Academic conference presentation
1.	2019/12/11	An SoC-FPGA-Based Micro UGV with Localization and Motion Planning (2019 International Conference on Field-Programmable Technology (FPT'19), pp.469-472, DOI 10.1109/FPT.2019.00095)
2.	2019/06/06	a Platform of Micro UGV for Small Scale Autonomous Driving System Using SoC FPGA (10th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART2019))
3.	2019/03/17	Example-based Face-image Restration for Block-noise Reduction (3rd International Conference on Frontiers of Image Processing (ICFIP2018), 15-P102)
4.	2019/01/20	Improved Face Image Super-resolution with Restricted Patch-searching Area (4th International Conference on Multimedia and Image Processing (ICMIP2019), 6-A0007, pp.29-35)
5.	2018/12/12	a Platform on All-Programmable SoC for Micro Autonomous Robots (2018 International Conference on Field-Programmable Technology (FPT'18), pp.406-409, DOI: 10.1109/FPT.2018.00085)
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