Researcher Database

（Last updated : 2025-04-07 14:10:57）　

YAMASHITA Shigeru

Department / Course College of Information Science and Engineering Department of Information Science and Engineering

Title / Position Professor

Scopus Paper Info
Paper Count: 157 Citation: 1252 h-index: 18

Click to view the Scopus page. The data was downloaded from Scopus API on Apr 28, 2025. via http://api.elsevier.com and http://www.scopus.com .

Other Affiliations
1.	Graduate School of Information Science and Engineering
2.	Research Organization of Science and Technology VLSI Center

Academic background
1.	2001/07 Degree Acquisition	│ Kyoto University Ph.D. in information science
2.	～1993/03	Department of Information Science │ Faculty of Engineering │ Kyoto University │ Graduated
3.	～1995/03	Master Course │ Information Science │ Graduate School, Division of Engineering │ Kyoto University │ Completed

Business career
1.	2012/04/01	Visiting Professor │ │ National Institute of Informatics

Committee and society
1.	2019 ～	IEEE Editorial Board Member of IEEE Circuits and Systems Magazine (CAS-M)
2.	2019 ～ 2020	IEICE Transactions A Special Section on Circuits and Systems 2020 Guest Associate Editor
3.	2020	IEEE Design, Automation & Test in Europe (DATE) 2020 Technical Program Committee Member
4.	2019	IEEE The Selection Committee for DATE PhD Forum 2020
5.	2018	IEEE The Selection Committee for DATE PhD Forum 2019
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Research activities
1.		Association for Computing Machinery
2.		The Institute of Electrical and Electronics Engineers (IEEE)
3.		The Information Processing Society of Japan
4.		The Institute of Electronics, Information and Communication Engineers (IEICE)

Subject of research
1.	Design and Utilization of New Type Computers
2.	Reconfigurable Computing
3.	Quantum Computing
4.	Biochip Design

Research summary
A research on how to configure a new computer and the design method Present stored-program computers have been amazingly developed since only about 50 years ago when they were invented. However, it seems to be impossible that they will develop, if they remain adopting this method. Firstly, the increase of power consumption of the computer and the decrease of the reliability of the computer as hardware have been problematic. In addition, we cannot expect the improvement of the performance due to the miniaturization of CMOS transistors in principle as we have achieved so far. I am engaged in the research on how to configure the innovative computers, how to use them, and the design methods to overcome the problems. Therefore, I am researching 2 subjects. The first one is to consider a method different from the previous one above the circuit design and architecture levels while I lay the foundations on the digital circuits by the CMOS technology that is widely used. For example, I am advancing the research on how to use hardware for which the logics such as FPGA is rewritable, the computing method using the GPUs different from the existing CPUs and the configuration method by which the computer can operate normally if the part of the circuit is physically broken down. The second one is to consider the possibilities of the computers based on a quite different computing principle from the existing CMOS technology and the configuration method. For example, concerning the quantum computation using the quantum state, I am researching the utilization method and the circuit design method. In addition, concerning the bio-computing that is expected to perform a reliable computation with a low power consumption, I am advancing the basic research on the circuit configuration method.

Present specialized field
Theory of informatics, Computer system, High performance computing (Keyword：Dependable Computing, Low Power, Logic Circuit Design, Reversible Logic Synthesis, GPGPU, Reconfigurable Computing, Quantum Computing, Biochip Design)

Books
1.	2017	電子情報通信学会 100年史 │ ,pp.D 情報・システム第1章コンピュータシステム 1.2 計算理論，並列・分散計算処理の節

Papers
1.	2025/04	Leveraging Different Boolean Function Decompositions to Reduce T-Count in LUT-based Quantum Circuit Synthesis │ IEICE Transactions on Information and Systems │ Vol. E108-D (4),pp.To Appear
2.	2025/04	Loading-Aware Mixing-Efficient Sample Preparation on Programmable Microfluidic Device, │ 2025 Design, Automation & Test in Europe Conference & Exhibition (DATE) │ ,pp.(To Appear)
3.	2025/01	Reducing T-Count in Quantum Circuits Using Alternate Forms of the Relative Phase Toffoli Gate │ IEICE Transactions on Fundamentals of Electronics │ Vol.E108-A (2),pp.1-10
4.	2024/08	An Efficient Cost Reduction Method By Reusing Intermediate Droplets in MEDA Biochips │ Proc. of International SoC Design Conference (ISOCC) │ ,pp.ET2-1
5.	2024/08	An Efficient Error Correction Method for DMFBs with Node Redundancy Considering Node Levels │ Proc. of International SoC Design Conference (ISOCC) │ ,pp.PS-17
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Academic conference presentation
1.	2024/10/22	Improving Mapping to Nearest Neighbor Architecture by Using Gaussian Elimination-based Method by Changing Qubits’ Order
2.	2024/10/22	Utilizing Don’t-Cares to Minimize CNOTs in Synthesizing NNA Compliant Quantum Circuits
3.	2023/11/16	Circuit division based on reinforcement learning to optimize Steiner-Gauss elimination for NNA-compliant quantum circuit synthesis
4.	2023/11/16	Leveraging different Boolean function decompositions to optimize LUT-based quantum circuit synthesis
5.	2023/11/16	Optimal Mapping to Nearest-Neighbor Architectures by Appling Simulated Annealing-based Gaussian Elimination Iterator
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Winning science prize
1.	2018/03	The 16th Workshop on Synthesis And System Integration of Mixed Information technologies Best Paper Award
2.	2014/01	ASP-DAC ASP-DAC 2014 Best Paper Candidate
3.	2013	IEEE IEEE Senior Member
4.	2011/03	2010 IPSJ Yamashita SIG Research Award
5.	2011/03	Marubun Academic Achievement Award of the Marubun Research Promotion Foundation
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Grants-in-Aid for Scientific Research -KAKENHI-
1.	2020/11 ～ 2025/03	NA │ Grant-in-Aid for Transformative Research Areas（A）
2.	2020/11 ～ 2025/03	NA │ Grant-in-Aid for Transformative Research Areas（A）
3.	2020/04 ～ 2024/03	NA │ Grant-in-Aid for Scientific Research(B)
4.	2020/04 ～ 2025/03	NA │ Grant-in-Aid for Scientific Research(A)
5.	2018/06 ～ 2021/03	NA │ etc.
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E-Mail Address

Department laboratory expense researcher number
30362833

researchmap Researcher code
5000067559

External Researcher ID
ORCID ID
0000-0002-2279-4644