研究者学術情報データベース

フジノ　タケシ
藤野　毅
FUJINO Takeshi

所属理工学部電子情報工学科

職名教授

論文
1.	2023/03/27	Practical aspects on non-profiled deep-learning side-channel attacks against AES software implementation with two types of masking countermeasures including RSM │ Journal of Cryptographic Engineering │ (共著)
2.	2023/03	Exploring Effect of Residual Electric Charges on Cryptographic Circuits : Extended Version │ IEICE TRANS. FUNDAMENTALS. │ E106-A (3),281-293頁 (共著)
3.	2023/03	Improving Robustness of Adversarial Examples Generated by Fault Injection Attack on MIPI │ 2023 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing │ (共著)
4.	2023/03	Profiling Deep Learning Side-channel Attacks using Multi-label against AES circuits with RSM Countermeasure │ E106A (3),294-305頁 (共著)
5.	2023/03	RGB-FIR Object Detection Considering Camera-to-Camera Misalignment │ 2023 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing │ (共著)
6.	2023/01/25	Fundamental Study of Adversarial Examples Created by Fault Injection Attack on Image Sensor Interface │ 2022 Asian Hardware Oriented Security and Trust Symposium (AsianHOST) │ (共著)
7.	2022/09/24	Towards Isolated AI Accelerators with OP-TEE on SoC-FPGAs │ LNCS (13285),200-217頁 (共著)
8.	2022/08	Deep Learning Side-Channel Attacks against Hardware-Implemented Lightweight Cipher Midori 64 │ The 4th International Symposium on Advanced Technologies and Applications in the Internet of Things │ (共著)
9.	2022/08	Deep Learning-Based Side-Channel Attacks against Software-Implemented RSA using Binary Exponentiation with Dummy Multiplication │ The 4th International Symposium on Advanced Technologies and Applications in the Internet of Things │ (共著)
10.	2022/03	Adversarial Scan Attack against Scan Matching Algorithm for Pose Estimation in LiDAR-Based SLAM │ IEICE TRANS. FUNDAMENTALS. │ E105-A (3),326-335頁 (共著)
11.	2022/03	Experimental Study of Fault Injection Attack on Image Sensor Interface for Triggering Backdoored DNN Models │ IEICE TRANS. FUNDAMENTALS. │ E105–A (3),336-343頁 (共著)
12.	2022/03	Fault Injection Attacks Utilizing Waveform Pattern Matching against Neural Networks Processing on Microcontroller │ IEICE TRANS. FUNDAMENTALS. │ E105 (3),300-310頁 (共著)
13.	2021/12	Deep Learning Side-Channel Attacks against Lightweight SCA Countermeasure RSM-AES │ Asian Hardware Oriented Security and Trust Symposium (AsianHOST) 2021 │ (共著)
14.	2021/11	Backdoor Attack on Deep Neural Networks Triggered by Fault Injection Attack on Image Sensor Interface │ ATTACKS AND SOLUTIONS IN HARDWARE SECURITY 2021 │ (共著)
15.	2021/11	Practical Aspects on Non-profiled Deep-learning Side-channel Attacks against AES software implementation with two types of masking countermeasures including RSM │ ATTACKS AND SOLUTIONS IN HARDWARE SECURITY 2021 │ (共著)
16.	2021/10	Area-Efficient Post-Processing Circuits for Physically Unclonable Function with 2-Mpixel CMOS Image Sensor │ Sensors │ 21 (6079),1-13頁 (共著)
17.	2021/10	Towards Trusted IoT Sensing Systems: Implementing PUF as Secure Key Generator for Root of Trust and Message Authentication Code │ Hardware and Architectural Support for Security and Privacy (HASP) 2021 │ (共著)
18.	2021/10	エッジAIデバイスのハードウェアセキュリティ │ 電子情報通信学会基礎・境界ソサイエティ Fundamentals Review │ 15 (2),88-100頁 (共著)
19.	2021/07/09	Timing Black-Box Attacks: Crafting Adversarial Examples through Timing Leaks against DNNs on Embedded Devices │ IACR Transactions on Cryptographic Hardware and Embedded Systems │ 2021 (3),149-175頁 (共著)
20.	2021/06	Model Evasion Attacks Against Partially Encrypted Deep Neural Networks in Isolated Execution Environment │ 2nd workshop on Artificial Intelligence in Hardware Security in conjunction with ACNS 2021 │ LNCS (12809),78-95頁 (共著)
21.	2021/06	Towards Trained Model Confidentialityand Integrity Using Trusted ExecutionEnvironments │ 2nd workshop on Artificial Intelligence in Hardware Security in conjunction with ACNS 2021 │ LNCS (12809),151-170頁 (共著)
22.	2021/01/01	Adversarial Black-Box Attacks with Timing Side-Channel Leakage │ IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences │ E104-A (1),143-151頁 (共著)
23.	2021/01	Adversarial Black-Box Attacks with Timing Side-Channel Leakage │ IEICE TRANS. FUNDAMENTALS │ VOL.E104–A (1),143-151頁 (共著)
24.	2021/01	Model Reverse-Engineering Attack against Systolic-Array-Based DNN Accelerator Using Correlation Power Analysis │ VOL.E104–A (1),152-161頁 (共著)
25.	2020/11	Disabling Backdoor and Identifying Poison Data by using Knowledge Distillation in Backdoor Attacks on Deep Neural Networks │ 10.1145 (3411508.3421375),117-127頁 (共著)
26.	2020/10/27	Deep learning side-channel attack against hardware implementations of AES │ Microprocessors and Microsystems │ (共著)
27.	2020/09	Model Reverse-Engineering Attack using Correlation Power Analysis against Systolic Array Based Neural Network Accelerator │ 2020 IEEE International Symposium on Circuits and Systems (ISCAS) │ 10.1109 (ISCAS45731.2020.9180580),1-5頁 (共著)
28.	2020/08/18	Simple electromagnetic analysis attack based on geometric leak on ASIC implementation of ring-oscillator PUF │ Journal of Cryptographic Engineering │ (共著)
29.	2020/07	Black-Box Adversarial Attack against Deep Neural Network Classifier Utilizing Quantized Probability Output │ Journal of Signal Procesing │ 24 (4),145-148頁 (共著)
30.	2020/07	Countermeasure against Backdoor Attack on Neural Networks Utilizing Knowledge Distillation │ Journal of Signal Procesing │ 24 (4),141-144頁 (共著)
31.	2020/03	Black-Box Adversarial Attack Utilizing Quantized Probability Output against Deep Neural Network Classifier │ RISP International workshop on Nonlinear Circuit, computer and Signal Processing │
32.	2020/03	Countermeasure against Backdoor Attack on Neural Networks Utilizing Knowledge Distillation │ RISP International workshop on Nonlinear Circuit, computer and Signal Processing │
33.	2020/03	Dependency Evaluation between Performance Metrics and Response-Bit Length of a CIS-PUF │ RISP International workshop on Nonlinear Circuit, computer and Signal Processing │
34.	2020/03	Detecting Backdoor Attacks on Deep Neural Networks by Saliency Map Clustering │ RISP International workshop on Nonlinear Circuit, computer and Signal Processing │
35.	2019/11	Simple Electromagnetic Analysis Attacks based on Geometric Leak on an ASIC Implementation of Ring-Oscillator PUF │ Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop │ ,13-21頁 (共著)
36.	2019/09	Deep Learning Side-Channel Attack Against Hardware Implementations of AES │ 2019 22nd Euromicro Conference on Digital System Design (DSD) │ ,261-268頁
37.	2019/06	Model-Extraction Attack against FPGA-DNN Accelerator Utilizing Correlation Electromagnetic Analysis │ 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) │ (共著)
38.	2019/03	Study of Countermeasure Using Time-Series Data against Physical Spoofing Attack on Range Sensor │ RISP International workshop on Nonlinear Circuit, computer and Signal Processing │
39.	2019/03	Study of Ultrasonic-Range-Sensor System with Resistance to Spoofing Attack │ RISP International workshop on Nonlinear Circuit, computer and Signal Processing │
40.	2019/03	The Effect of High Dynamic Range Images on Image Recognition Using Deep Learning │ RISP International workshop on Nonlinear Circuit, computer and Signal Processing │
41.	2018/03	Bedside Event Real-time Recognition Using Low Resolution Infrared Array Sensor with Recurrent Convolutional Neural Network │ RISP International workshop on Nonlinear Circuit, computer and Signal Processing │
42.	2018/03	RGB-FIR Camera Sensor Fusion for Robust Object Recognition with Deep Neural Network │ RISP International workshop on Nonlinear Circuit, computer and Signal Processing │
43.	2017/03	Fast Face-Detection Algorithm Assisted with Infrared Array Sensor │ RISP International workshop on Nonlinear Circuit, computer and Signal Processing │
44.	2017/03	Human Detection by Convolutional Neural Network in Low Resolution Infrared Image │ RISP International workshop on Nonlinear Circuit, computer and Signal Processing │
45.	2017/03	Spy-photo prevention system using flicker-noise with LED lighting │ RISP International workshop on Nonlinear Circuit, computer and Signal Processing │
46.	2017	Hierarchical-Masked Image Filtering for Privacy-Protection │ IEICE Transactions on Information and Systems │ E100-D (10),2327-2338
47.	2016/11	Proposal and Implementation of Key Exchange Protocol for Vehicle’s Inner Network based on Common Key Encryption using PUF as Key Storage │ Embedded Security in Cars Europe 2016 │
48.	2016/07	Low Power AFE Circuit Supporting IR Array Sensor for Human Detection │ Journal of Signal Processing │ Vol. 20 (No. 4),133-136 (共著)
49.	2016/03	1/f Fluctuation-Based Visible Light Beacon for Spy-Photo Prevention System │ 2016 RISP International Workshop on NCSP │ (共著)
50.	2016/03	Design of Low Power AFE Circuit supporting IR Array Sensor for Human Detection │ 2016 RISP International Workshop on NCSP │ (共著)
51.	2016/03	Information Including Flicker Noise with LED Lighting for Preventing Spy-Photos │ 2016 RISP International Workshop on NCSP │ (共著)
52.	2016/03	Morphological Pattern Spectrum-Based Image Manipulation Detection for Compression Data │ 2016 RISP International Workshop on NCSP │ (共著)
53.	2016/03	Study of Human Event Detection Algorithm by Infrared Array Sensor on Low Power Consumption Image Sensor Node │ 2016 RISP International Workshop on NCSP │ (共著)
54.	2016/02	耐タンパセキュリティハードウェアの開発と車載システムへの応用 │ 電子情報通信学会論文誌(A) │ Vol.J99-A (No.2),83-93 (共著)
55.	2015/07	Digital Image Forensics Using Morphological Pattern Spectrum │ Journal of Signal Processing │ Vol 19 (No.4),159-162 (共著)
56.	2015/05	Reversing Stealthy Dopant-Level Circuits │ Journal of Cryptographic Engineering │ Vol. 5 (Issue 2),85-94 (共著)
57.	2015/05	Tamper-Resistant Authentication System with Side-Channel Attack Resistant AES and PUF using MDR-ROM │ International Symposium on Circuits and Systems (ISCAS) │ ,1462-1465 (共著)
58.	2015/04	ハードウェアトロイ検証環境の開発と暗号回路を用いた実装及び評価 │ 電子情報通信学会論文誌 (A) │ vol. J98-A (no. 4),313-326 (共著)
59.	2015/03	A Study of Normally-off Scheme for CMOS Analog by Bias Cutting Control │ 2015 RISP International Workshop on NCSP │ ,302-305 (共著)
60.	2015/03	Attack Alert Circuit for Hardware Trojan in an Embedded System │ 2015 RISP International Workshop on NCSP │ ,365-368 (共著)
61.	2015/03	Morphological Pattern Spectrum-Based Image Manipulation Detection │ 2015 RISP International Workshop on NCSP │ ,591-595 (共著)
62.	2015/03	Power Analysis Attacks on AES using RSM Countermeasure │ 2015 RISP International Workshop on NCSP │ ,306-309 (共著)
63.	2015/03	Side Channel Attacks on 64-bit Lightweight Block Ciphers-PRESENT, TWINE, and Piccolo │ 2015 RISP International Workshop on NCSP │ ,298-301 (共著)
64.	2015/03	The Intermittent-Operation Control LSI for Ultra-Low-Power Camera: Green Smart Secure Eyes │ 2015 RISP International Workshop on NCSP │ ,377-380 (共著)
65.	2014/07	Via-Programmable Structured ASIC "VPEX3S" for High-Speed Application │ Journal of Signal Processing │ Vol. 18 (No. 4),161-164 (共著)
66.	2014/06	Side-channel attack resistant AES cryptographic circuits with ROM reducing address-dependent EM leaks │ IEEE International Symposium on Circuits and Systems (ISCAS) │ ,2547-2550 (共著)
67.	2014/03	A cropping robust digital watermarking algorithm using morphological wavelet transform based on max-plus algebra │ 2014 RISP International Workshop on NCSP │ ,737-740 (共著)
68.	2014/03	Development of compression tolerable and highly implementable watermarking method for mobile devices │ IEICE Transactions on Information & Systems │ vol. E97-D (no. 3),593-596 (共著)
69.	2014/03	Hardware Controller of camera sensor node using IR array sensor and CMOS image sensor for ultra-low-power operation │ 2014 RISP International Workshop on NCSP │ ,749-752 (共著)
70.	2014/03	Human Detection Algorithm using low-resolution Infrared Image in Wireless Sensor Networks │ 2014 RISP International Workshop on NCSP │ ,645-648 (共著)
71.	2014/03	Improved Via-Programmable Structured ASIC VPEX3S and Its Evaluation │ 2014 RISP International Workshop on NCSP │ ,97-100 (共著)
72.	2014/03	Lightweight privacy protetion in intermittent-sensing image sensor node │ 2014 RISP International Workshop on NCSP │ ,473-476. (共著)
73.	2014/03	Tamper-Resistant AES Cryptographic Circuit utilizing Hybrid Masking Dual-Rail ROM │ 2014 RISP International Workshop on NCSP │ ,101-104 (共著)
74.	2014/01	On measurable side-channel leaks inside ASIC design primitives │ J. Cryptographic Engineering │ 4 (1),59-73 (共著)
75.	2014/01	Security Evaluation of RG-DTM PUF using Machine Learning Attacks │ IEICE TRANSACTIONS on Fundamentals │ E97-A (1),275-283 (共著)
76.	2014/01	Unified Coprocessor Architecture for Secure Key Storage and Challenge-Response Authentication │ IEICE TRANSACTIONS on Fundamentals │ E97-A (1),264-274 (共著)
77.	2013/12	クロック変動機構を用いた耐タンパアーキテクチャ │ 電気学会論文誌Ｃ │ 133 (12),2134-2142 (共著)
78.	2013/10	A Stable Key Generation from PUF Responses with a Fuzzy Extractor for Cryptographic Authentications │ IEEE 2nd Global Conference on Consumer Electronics (GCCE) │ ,525-527 (共著)
79.	2013/10	Evaluation of On-Chip Decoupling Capacitor’s Effect on AES Cryptographic Circuit │ Synthesis And System Integration of Mixed Information technologies (SASIMI) 2013 │ ,13-18 (共著)
80.	2013/10	PowerAnalysis Resistant IP Core using IO-Masked Dual-Rail ROM for Easy Implementation into Low-Power Area-Efficient Cryptographic LSIs │ Synthesis And System Integration of Mixed Information technologies (SASIMI) 2013 │ ,82-87 (共著)
81.	2013/08	Cipher-destroying and secret-key-emitting hardware Trojan against AES core │ International Midwest Symposium on Circuits and Systems (MWSCAS2013) │ ,408-411 (共著)
82.	2013/08	Development of effective information-hiding method for embedded systems │ International Midwest Symposium on Circuits and Systems (MWSCAS2013) │ ,1298-1301 (共著)
83.	2013/08	Hierarchical image-scrambling method with scramble-level controllability for privacy protection │ International Midwest Symposium on Circuits and Systems (MWSCAS2013) │ ,1371-1374 (共著)
84.	2013/08	On Measurable Side-Channel Leaks Inside ASIC Design Primitives │ Lecture Notes in Computer Science, CHES2013 │ 8086,159-178 (共著)
85.	2013/07	Morphological pattern spectrum-based objects detection for protecting privacy │ Journal of Signal Processing │ 17 (4),pp.155-158 (共著)
86.	2013/04	The implementation of DES circuit on via-programmable structured ASIC architecture VPEX3 │ VLSI Design, Automation, and Test 2013 │ (共著)
87.	2013/03	An Arbiter Circuit utilizing Time to Digital Converter Scheme for the RG-DTM PUF │ 2013 RISP International Workshop on NCSP │ ,pp.209-212 (共著)
88.	2013/03	Development of Low-power Camera Sensor Node using Infrared Array Sensor and CMOS Image Sensor │ 2013 RISP International Workshop on NCSP │ ,pp.508-511 (共著)
89.	2013/03	Efﬁcient Evaluation Method of Tamper Resistant AES Cryptographic Circuits │ 2013 RISP International Workshop on NCSP │ ,pp.213-216 (共著)
90.	2013/03	Low Power Sensor System Using Smart Analog under Normally Off Operation │ 2013 RISP International Workshop on NCSP │ ,pp.644-647 (共著)
91.	2013/03	Use of Morphological Pattern Spectrum to Detect Objects and Protect Privacy │ 2013 RISP International Workshop on NCSP │ ,pp.377-380 (共著)
92.	2013/03	ストリーム暗号CryptMTのデータ並列処理による高速化手法及びSIMD型組込みプロセッサによる実装と評価 │ 電子情報通信学会論文誌 D │ J96-D (3),495-505 (共著)
93.	2013/02	Hybrid Masking using Intra-Masking Dual-Rail Memory on LUT for SCAResistant AES Implementation on FPGA │ 21st ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) │ ,pp.266-267 (単著)
94.	2012/12	Via Programmable Structured ASIC Architecture “VPEX3” and CAD Design System │ IEICE TRANSACTIONS on Fundamentals │ Vol.E95-A (No. 12),pp.2182-2190 (共著)
95.	2012/12	アーキテクチャを考慮した複数エラーの差分推定に基づくフォールト解析とその評価 │ Vol. 132 (No. 12),1888-1896 (共著)
96.	2012/10	Development of Evaluation Environment for Physical Attacks against Embedded Devices │ The 1st International Conference on Consumer Electronics (GCCE2012) │ ,591-594 (共著)
97.	2012/09	Efficient DPA-Resistance Verification Method with Smaller Number of Power Traces on AES Cryptographic Circuit │ Euromicro Conference on Digital System Design (DSD) │ ,735-738 (共著)
98.	2012/09	Improved Via-Programmable Structured ASIC VPEX3 and Its Evaluation │ IEICE TRANSACTIONS on Fundamentals │ Vol.E95-A (No.9),pp.1518-1528 (共著)
99.	2012/07	Experimental Security Evaluation against Machine Learning Attacks on RG-DTM PUF │ The 27th International Technical Conference on Circuits/Systems, Computers and Communications │ ,C-T1-02 (共著)
100.	2012/07	Highly-parallel Triple DES processing with Massive- Parallel SIMD Matrix evaluation board │ The 27th International Technical Conference on Circuits/Systems, Computers and Communications │ ,F-T1-04 (共著)
101.	2012/04	High Uniqueness Arbiter-Based PUF Circuit Utilizing RG-DTM Scheme for Identification and Authentication Applications │ IEICE TRANSACTIONS on Electronics │ Vol. E95-C (No.4),pp.468-477 (共著)
102.	2012/03	Highly-parallel AES processing for five confidentiality modes with massive-parallel SIMD matrix processor │ The 17th Workshop on Synthesis And System Integration of Mixed Information technologies │ ,367 - 371 (共著)
103.	2012/03	Highly-Parallel Watermarking Implimentation for Max-Plus Algebra Morphological Wavelet Transform with Massive-Parallel SSIMD Matrix Evaluation Board │ 2012 RISP International Workshop on NCSP │ (共著)
104.	2012/03	Performance Comparison of RG-DTM PUF and Arbiter-based PUFs │ The 17th Workshop on Synthesis And System Integration of Mixed Information technologies │ ,82 - 87 (共著)
105.	2012/03	SIMD型組込みプロセッサによる擬似乱数生成アルゴリズムの並列処理実装とその評価 │ 電子情報通信学会論文誌 D │ Vol.J95-D (3),376-386 (共著)
106.	2012/03	The Development of CAD System for Via Programmable Structured ASIC VPEX3 │ The 17th Workshop on Synthesis And System Integration of Mixed Information technologies │ ,470 - 475 (共著)
107.	2012/03	多重化ユニットを用いた物理的複製不可能関数とその実装評価 │ 電気学会論文誌Ｃ │ Vol.132 (3),364-373 (共著)
108.	2012/02	Intra-Masking Dual-Rail Memory on LUT Implementation for Tamper Resistant AES on FPGA │ 20th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) │ ,1-10 (単著)
109.	2011/11	上流設計工程でのサイドチャネル攻撃に対する耐タンパ検証手法とその評価 │ 電気学会論文誌Ｃ │ Vol.131 (11),1940-1949 (共著)
110.	2011/06	Decomposition/Reconstruction Acceleration of Max-Plus Algebra-Based Morphological Wavelet Transform with Massive-Parallel SIMD Matrix Mobile Processor │ Journal of Signal Processing │ 15 (6),425-434 (共著)
111.	2011/06	Highly-parallel Bitslice AES Implementation with Massive-parallel SIMD Matrix for Mobile Processor │ Proceeding of The 26th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) │ ,237-240 (共著)
112.	2011/06	Implementation and Verification of DPA-Resistant Cryptographic DES Circuit using Domino-RSL │ Proceeding of The IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) │ ,28-33 (共著)
113.	2011/05	The Arbiter-PUF with High Uniqueness utilizing Novel Arbiter Circuit with Delay-Time Measurement │ Digest Paper of The IEEE International Symposium on Circuits and Systems (ISCAS) │ ,2325-2328 (共著)
114.	2011/03	AES Side Channel Attack Using Final to First Rounds Hamming Distance │ 2011 RISP International Workshop on NCSP │ ,182-185 (共著)
115.	2010/11	Placement Tool Dedicated for a Via-programmable Logic Device VPEX │ Proc. of 23rd International Conference on Computer Applications in Industry and Engineering │ ,21-25 (共著)
116.	2010/10	LSI Implementation Method of DES Cryptographic Circuit utilizing Domino-RSL Gate Resistant to DPA Attack │ The 16th Workshop on Synthesis And System Integration of Mixed Information technologies │ ,196 - 201 (共著)
117.	2010/06	マルチファンクションプログラマブルSOI-演算メモリMFPM │ 電子情報通信学会論文誌 D │ Vol.J93-D (6),931-948 (共著)
118.	2009/12	Via-programmable Logic Array VPEX2 with Configurable DFF using 2 Logic Elements │ The 12th International Symposium on Integrated Circuits │ ,21-24 (共著)
119.	2009/03	Interconnect Utilization of the VPEX Via-Programmable Structured ASIC │ The 15th Workshop on Synthesis And System Integration of Mixed Information technologies │ ,330-334 (共著)
120.	2008/04	Regular Fabric of Via Programmable Logic Device using EXclusive-or Array (VPEX) for EB Direct Writing │ IEICE TRANS. on Electronics │ E91-C (4),509-516 (共著)
121.	2006/11	An Embedded Programmable Logic Matrix (ePLX) for flexible functions on SoC │ IEEE Asian Solid-State Circuit Conference │ ,219 - 222 (共著)
122.	2006/05	Shot Number Estimation for EB Direct Writing for Logic LSI Utilizing Character-Build Standard-Cell Layout Technique │ Proc. SPIE, Photomask and Next-Generation Lithography Mask Technology XIII │ 6283,1-8 (共著)
123.	2006	Shot Number Estimation for EB Direct Writing for Logic LSI Utilizing Character-Build Standard-Cell Layout Technique │ Proceedings of SPIE │ 6283 (2M),1-8 (共著)
124.	2005/05	Character-Built Standard-Cell Layout Technique for High-Throughput Character-Projection EB lithography │ Proc. SPIE, Photomask and Next-Generation Lithography Mask Technology XII │ 5853,160-167 (共著)
125.	2003/02	A High Density Memory for Soc with a 143MHz SRAM Interface Using Sense-Synchronized Read/Write │ 2003 IEEE International Solid State Circuit Conference (ISSCC) │ ,306-307 (共著)
126.	2003	0.15～0.13μm DRAM混載ロジック技術 │ 三菱電機技報 │ 77,54-57 (共著)
127.	2003	A High Density Memory for Soc with a 143MHz SRAM Interface Using Sense-Synchronized Read/Write │ IEEE J. Solid-State Circuits │ 38 (11),1967-1973 (共著)
128.	2003	A Low Power Embedded DRAM Macro for Battery-Operated LSIs │ IEICE Transactions on Fundamentals │ E86-A (38),2991-3000 (共著)
129.	2002	A 0.18um 32Mb Embedded DRAM Macro for 3-D Graphic Controller │ E85-C (9),1697-1708 (共著)
130.	2000/02	A 56.8GB/s 0.18um embedded DRAM macro with dual port sense amplifier for 3D graphics controller │ 2000 IEEE International Solid State Circuit Conference (ISSCC) │ ,394-395 (共著)
131.	2000	0.18μm eDRAMコアの開発による0.18μm DRAM混載システムLSIコア技術の確立 │ 三菱電機技報 │ 74,48-53 (共著)
132.	1998/06	Multi Gbit-scale Partially Frozen (PF) NAND DRAM with SDRAM Compatible Interface │ Symposium on VLSI Circuits Digest of Technical Papers │ ,96-99 (共著)
133.	1998	256MビットDRAMチップ │ 三菱電機技報 │ 72,32-35 (共著)
134.	1998	化学増幅ポジ型３成分系電子線レジストの設計と開発 │ 高分子論文集 │ 55,231-242 (共著)
135.	1997/02	A 1.2V to 3.3V wide-voltage-range DRAM with 0.8V array operation │ 1997 IEEE International Solid State Circuit Conference (ISSCC) │ ,66-67 (共著)
136.	1997	A 1.2- to 3.3-V wide voltage-range/low-power DRAM with a charge-transfer presensing scheme │ IEEE J. Solid-State Circuits │ 32 (11),1721-1727 (共著)
137.	1996/02	Comparison of Standard and Low-Dose Separation-by-Implanted-Oxygen Substrates for 0.15 µm SOI MOSFET Applications │ Jpn. J. Appl. Phys. │ 35 (2B),983-987 (共著)
138.	1996	Electron Beam Direct Writing Techniques for the Development of Sub-Quarter-Micron Devices │ Jpn. J. Appl. Phys. │ 35 (12A),6320-6327 (共著)
139.	1994/12	Application of Proximity Effect Correction Using Pattern-Area-Density to Patterning on a Heavy Metal Substrate and the Cell-Projection Exposure │ Jpn.J.Appl.Phys │ 33 (12B),6946-6952 (共著)
140.	1994/12	Proximity Effect Correction for 1:1 X-ray Mask Fabrication │ Jpn. J. Appl. Phys. │ 33 (12B),6976-6982 (共著)
141.	1993/11	Chemical amplification EB positive process free from surface insoluble layer │ J. Vac. Sci. Technol. │ B11 (6),2773 (共著)
142.	1992/12	Sputtered W-Ti Film for X-ray Mask Absorber │ Jpn. J. Appl. Phys. │ 31 (12B),4210-4214 (共著)
143.	1992	Novel Electron Beam Direct Writing Technique for the Hole Pattern of Quarter Micron Devices │ Jpn. J. Appl. Phys. │ 31 (30),4262 (共著)
144.	1992	X-ray Mask Fabrication Process Using Cr Mask and ITO Stopper in the Dry Etching of W Absorber │ Jpn. J. Appl. Phys. │ 31,4086 (共著)
145.	1991/02	Fabrication of 0.25-μm Patterns on a Membrane Substrate-based X-ray Absorber │ Jpn. J. Appl. Phys. │ 30 (2B),3058-3064 (共著)
146.	1990/11	Novel process using x-ray lithography for T-shaped gate patterns │ J. Vac. Sci. Technol. │ B6 (6),1535-1538 (共著)
147.	1990/11	The surface silylating process using chemical amplification resist for electron beam lithography │ J. Vac. Sci. Technol. │ B8 (6),1808 (共著)
148.	1990	Electron Beam Direct Writing Technologies for 0.3-μm ULSI Devices │ Jpn. J. Appl. Phys. │ 29,2584 (共著)
149.	1989/11	Sub-0.2-um lithography by using a variable-shaped electron beam assisted by a focused ion beam process │ J. Vac. Sci. Technol. │ B7,2044 (共著)
150.	1988/11	Hybrid lithography of a focused ion beam and an electron beam for the fabrication of a GaAs field effect transistor with a mushroom gate │ J. Vac. Sci. Technol. │ B6,1828 (共著)