Researcher Database

IZUMI Tomonori

Department / Course College of Science and Engineering Department of Electronic and Computer Engineering

Title / Position Professor

Papers
1.	2021/03	A Demodulation Method Using a Gaussian Mixture Model For Unsynchronous Optical Camera Communication with On-off Keying │ Journal of Lightwave Technology │ 39,pp.1742-1755 (Co-authored)
2.	2019/03	Example-based Face-image Restration for Block-noise Reduction │ Journal of Image and Graphics │ 7 (1),pp.9-17 (Co-authored)
3.	2018/12	Face Image Super-Resolution with Adaptive Patch Size to Scaling Factor │ Journal of Image and Graphics │ 6 (2),pp.167-173 (Co-authored)
4.	2017/11	Example-based Face Image Super-resolution Taking into Consideration Correspondence of Facial Parts │ Trans. on Electrical and Electronic Engineering (TEEE-C) │ 12 (6),pp.917-924 (Co-authored)
5.	2016/02	Recognition of Oracular Bone Inscriptions Using Template Matching │ Int. J. of Computer Theory and Engineering │ 8 (1),pp.53-57 (Co-authored)
6.	2014	Combining ALU chaining with two-direction address renaming load value prediction │ Int. J. Advanced Mechatronic Systems │ 6 (1),pp.53-64 (Co-authored)
7.	2012/09	Images Up-scaling Algorithm Based on the Total Variation Method and Morphological Emphasizing │ 画像電子学会誌 │ 41 (5),pp.520-527 (Co-authored)
8.	2012/09	Expression Recognition Using LGDPHS Based Facial Key Parts │ 画像電子学会誌 │ 41 (5),pp.496-505 (Co-authored)
9.	2012/05	Age and Gender Estimation Using Global and Local Features with AAM and LGDPHS │ 画像電子学会誌 │ 41 (3),pp.262-269 (Co-authored)
10.	2008/12	Autonomous Repair Fault Tolerant Dynamic Reconfigurable Device │ IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences │ Vol.E91-A (No.12),pp.pp.3612-3621 (Co-authored)
11.	2007/04	A Simulation Platform for Designing Cell-Array-Based Self-Reconfigurable Architecture │ IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences │ Vol.E90-A (No.4),pp.pp.784-791 (Co-authored)
12.	2006/12	Fault Tolerant Dynamic Reconfigurable Device Based on EDAC With Rollback │ IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences │ Vol.E89-A (No.12),pp.pp.3652-3658 (Co-authored)
13.	2005/04	An Integrated Approach of Variable Ordering and Logic Mapping into LUT-Array-Based PLD │ IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences │ Vol.E88-A (No.4),pp.pp.907-914 (Co-authored)
14.	2003/05	Design Tools and Trial Design for PCA-Chip2 │ IEICE Trans. on Information and Systems │ Vol.E86-D (No.5),pp.pp.868-871 (Co-authored)
15.	2001/11	LUT-Array-Based PLD and Synthesis Approach Based on Sum of Generalized Complex Terms Expression │ IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences │ Vol.E84-A (No.11),pp.pp.2681-2689 (Co-authored)
16.	2000/12	Array-Based Mapping Algorithm of Logic Functions into Plastic Cell Architecture │ IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences │ Vol.E83-A (No.12),pp.pp.2538-2544 (Co-authored)
17.	1998/05	Air-Pressure Model and Fast Algorithms for Zero-Wasted-Area Layout of General Floorplan │ IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences │ Vol.E81-A (No.5),pp.pp.842-849 (Co-authored)
18.	1998/05	Computational Complexity Analysis of Set-Bin-Packing Problem │ IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences │ Vol.E81-A (No.5),pp.pp.857-865 (Co-authored)