Ritsumeikan University Researcher Database
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NAKAMURA Yukihiro
Department / Course
Research Organization of Science and Technology
Title / Position
Visiting Senior Researcher
Papers
1.
2011/05
Hardware Accelerator for Robust Object Tracking Using a Cascade Particle Filter │ Journal of Signal Processing │ 15 (3),pp.215-223 (Co-authored)
2.
2010/10
A Tile Based Reconfigurable Architecture with Dual ALU-Array/processor Operating
Mode Capability │ Proc. of SASIMI │ ,pp.454-459 (Co-authored)
3.
2009/11
Hardware Accelerator for Run-Time Learning Adopted in Object Recognition with Cascade Particle Filter │ IEICE Trans. on Fundamentals │ E92-A (11),pp.2801-2808 (Co-authored)
4.
2009/08
Efficient Memory Organization Framework for JPEG2000 Entropy Codec │ IEICE Trans. on Fundamentals │ E92-A (8),pp.1970-1977 (Co-authored)
5.
2009/02
An Asynchronous IEEE-754-Standard Single-Precision Floating-Point Divider for FPGA │ IPSJ Trans. on System LSI Design Methodology │ 2,pp.103-113 (Co-authored)
6.
2009/01
JPEG2000 high-speed SNR progressive decoding scheme │ International Journal of Computer Science and Network Security │ 9 (1),pp.62-68 (Co-authored)
7.
2008/12
Autonomous Repair Fault Tolerant Dynamic Reconfigurable Device │ IEICE Trans. on Fundamentals │ E91-A (12),pp.3612-3621 (Co-authored)
8.
2007/07
Automatic filter design for 3-D sound movement in embedded applications │ Acoustical Science and Technology │ 28 (4),pp.219-229 (Co-authored)
9.
2007/07
Evaluation of reliable multicast applications for large-scale contents delivery │ IEICE Trans. on Communications │ E90-B (10) (Co-authored)
10.
2007/04
A retargetable compiler for cell-array-based self-reconfigurable architecture │ International Journal of Computer Science and Network Security │ 7 (4),pp.131-139 (Co-authored)
11.
2007/04
A simulation platform for designing cell-array-based self-reconfigurable architecture │ IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences │ E90-A (4),pp.784-791 (Co-authored)
12.
2007/03
Efficient 3-D sound movement with time-varying IIR filters │ IEICE Trans. on Fundamentals │ E90-A (3),pp.618-625 (Co-authored)
13.
2007/03
Stochastic pedestrian tracking based on 6-stick skeleton model │ IEICE Trans. on Fundamentals │ E90-A (3),pp.606-617 (Co-authored)
14.
2007/02
Network processor for high-speed network and quick programming │ World Scientific, Journal of Circuits, Systems, and Computers │ 16 (1),pp.65-79 (Co-authored)
15.
2007/01
Pedestrian recognition suitable for night vision systems │ International Journal of Computer Science and Network Security │ 7 (1),pp.1-8 (Co-authored)
16.
2006/12
Fault tolerant dynamic reconfigurable device based on EDAC with rollback │ IEICE Trans. on Fundamentals │ E89-A (12),pp.3652-3658 (Co-authored)
17.
2006
Scalable design framework for JPEG2000 system architecture │ Intelligent Automation and Soft Computing │ 13 (3),pp.331-343 (Co-authored)
18.
2005/05
Design of realtime 3-D sound processing system │ IEICE Trans. on Information and Systems │ E88-D (5),pp.954-962 (Co-authored)
19.
2005/04
An integrated approach of variable ordering and logic mapping into LUT-array-based PLD │ IEICE Trans. on Fundamentals │ E88-A (4),pp.907-914 (Co-authored)