研究者学術情報データベース

トミヤマ　ヒロユキ
冨山　宏之
TOMIYAMA Hiroyuki

所属理工学部電子情報工学科

職名教授

論文
1.	2024/04	Dynamic Point-Pixel Feature Alignment for Multimodal 3D Object Detection │ IEEE Internet of Things Journal │ 11 (7),11327-11340頁 (共著)
2.	2024	Timing Issues on Power Side-Channel Leakage of AES Circuits Designed by High-Level Synthesis │ International Journal of Reconfigurable and Embedded Systems (Accepted) │ (共著)
3.	2023/11	A Deep Reinforcement Learning Approach to Droplet Routing for Erroneous Digital Microfluidic Biochips │ Sensors │ 23 (21) (共著)
4.	2023/11	Empirical Analysis of Power Side-Channel Leakage of High-Level Synthesis Designed AES Circuits │ International Journal of Reconfigurable and Embedded Systems │ 12 (3),305-319頁 (共著)
5.	2023/05	An Integer Programming Based Approach to Delivery Drone Routing under Load-Dependent Flight Speed │ Drones │ 7 (5) (共著)
6.	2023/03	An Architecture-level Analysis on Deep Learning Models for Low-Impact Computations │ Artificial Intelligence Review │ 56 (3),1971-2010頁 (共著)
7.	2023/03	Side Channel Power Analysis Resistance Evaluation of Masked Adders on FPGA │ International Journal of Reconfigurable and Embedded Systems │ 12 (1),97-112頁 (共著)
8.	2023/02	Fast and High-quality Monocular Depth Estimation with Optical Flow for Autonomous Drones │ Drones │ 7 (2) (共著)
9.	2022/11	Shape-Dependent Velocity based Droplet Routing on MEDA Biochips │ IEEE Access │ 10,122423-122430頁 (共著)
10.	2022/10	ILP-based and Heuristic Scheduling Techniques for Variable-Cycle Approximate Functional Units in High-Level Synthesis │ Computers │ 11 (10) (共著)
11.	2022/06	Optimizing the Deep Neural Networks by Layer-wise Refined Pruning and the Acceleration on FPGA │ Computational Intelligence and Neuroscience │ 2022 (共著)
12.	2022/05	Minimization of MEDA Biochip-Size in Droplet Routing │ Biosensors │ 12 (5) (共著)
13.	2022/04	Mouldable Fork-Join Task Scheduling Techniques with Inter and Intra-Task Communications │ International Journal of Embedded Systems │ 15 (1),69-81頁 (共著)
14.	2022/03	Pix2Pix-based Monocular Depth Estimation for Drones with Optical Flow on AirSim │ Sensors │ 22 (6) (共著)
15.	2022/03	Simultaneous Scheduling and Core-Type Optimization for Moldable Fork-Join Tasks on Heterogeneous Multicores │ IEICE Transactions on Fundamentals │ E105-A (3),540-548頁 (共著)
16.	2022/02	Feature Classification-Based Inclination Measurement for Industrial Assembly Platform │ Wireless Communications and Mobile Computing │ 2022 (共著)
17.	2022/02	Load and Wind Aware Routing of Delivery Drones │ Drones │ 6 (2) (共著)
18.	2021/12	A Survey of Convolutional Neural Networks - From Software to Hardware and the Applications in Measurement │ Measurement: Sensors │ 18 (共著)
19.	2021/11	Heuristic Algorithms for Dynamic Scheduling of Moldable Tasks in Multicore Embedded Systems │ International Journal of Reconfigurable and Embedded Systems │ 10 (3),157-167頁 (共著)
20.	2021/08	Energy-aware Routing of Delivery Drones under Windy Conditions │ IPSJ Transactions on System LSI Design Methodology │ 14,30-39頁 (共著)
21.	2021/06	A Methodology for Measuring Flight Speed of Drones in Indoor Environments │ Procedia Computer Science │ 187,322-328頁 (共著)
22.	2021/06	A Skeleton Analysis Based Fall Detection Method Using ToF Camera │ Procedia Computer Science │ 187,252-257頁 (共著)
23.	2021/06	Pneumonia Diagnosis on Chest X-Rays with Machine Learning │ Procedia Computer Science │ 187,42-51頁 (共著)
24.	2021/03	A Design Methodology for Approximate Multipliers in Convolutional Neural Networks: A Case of MNIST │ International Journal of Reconfigurable and Embedded Systems │ 10 (1),1-10頁 (共著)
25.	2021/01	Motion Estimation Based Inclination Measurement of the Assembly Platform │ International Journal of Advanced Mechatronic Systems │ 8 (4),155-165頁 (共著)
26.	2020/09	A Self-Learning Fall Detection System for Elderly Persons Using Depth Camera │ International Journal of Advanced Mechatronic Systems │ 8 (1),16-25頁 (共著)
27.	2020/08	A Dynamic Programming Algorithm for Energy-aware Routing of Delivery Drones │ IPSJ Transactions on System LSI Design Methodology │ 13,65-68頁 (共著)
28.	2020/08	Function-Level Module Sharing Techniques in High-Level Synthesis │ ETRI Journal │ 42 (4),527-533頁 (共著)
29.	2020/07	A Method of Japanese Ancient Text Recognition by Deep Learning │ Procedia Computer Science, Elsevier │ 174,276-279 (共著)
30.	2020/07	An Edge Computing Based Fall Detection System for Elderly Persons │ Procedia Computer Science, Elsevier │ 174,9-14 (共著)
31.	2020/07	Camera Motion Estimation Algorithm for IoT Devices based on Optimized Feature Tracking Method │ Procedia Computer Science, Elsevier │ 174,22-26 (共著)
32.	2020/07	Machine Learning Based Features Matching for Fatigue Crack Detection │ Procedia Computer Science, Elsevier │ 174,101-105 (共著)
33.	2020/02	A Branch-and-Bound Approach to Scheduling of Data-Parallel Tasks on Multicore Architectures │ International Journal of Embedded Systems, Inderscience Publishers │ 12 (1),125-135 (共著)
34.	2019/12	QoE-Constrained Concurrent Request Optimization Through Collaboration of Edge Servers │ IEEE Internet of Things Journal │ 6 (6),9951-9962 (共著)
35.	2019/10	Energy-Aware Scheduling of Malleable Fork-Join Tasks under a Deadline Constraint on Heterogeneous Multicores │ ACM SIGBED Review │ 16 (3),57-62 (共著)
36.	2019/10	ILP-based Scheduling for Malleable Fork-Join Tasks │ ACM SIGBED Review │ 16 (3),21-26 (共著)
37.	2019/09	Robust Self-Adaptation Fall-Detection System based on Camera Height │ Sensors, MDPI │ 19 (17) (共著)
38.	2019/08	A Genetic Algorithm for Scheduling of Data-Parallel Tasks on Multicore Architectures │ IPSJ Transactions on System LSI Design Methodology │ 12,74-77 (共著)
39.	2019/08	Communication-Aware Scheduling of Data-Parallel Tasks on Multicore Architectures │ IPSJ Transactions on System LSI Design Methodology │ 12,65-73 (共著)
40.	2019/07	A Constraint Programming Approach to Scheduling of Malleable Tasks │ International Journal of Networking and Computing │ 9 (2),131-146 (共著)
41.	2019/02	A HOG-SVM Based Fall Detection IoT System for Elderly Persons Using Deep Sensor │ Procedia Computer Science, Elsevier │ 147,276-282 (共著)
42.	2019/02	An OpenCL-based Software Framework for a Heterogeneous Multicore Architecture on Zynq-7000 SoC │ IPSJ Transactions on System LSI Design Methodology │ 12,46-49 (共著)
43.	2019/02	Design and Evaluation of Asymmetric and Symmetric 32-core Architectures on FPGA │ IPSJ Transactions on System LSI Design Methodology │ 12,42-45 (共著)
44.	2019/02	Three-States-Transition Method for Fall Detection Algorithm Using Depth Image │ Journal of Robotics and Mechatronics │ 31 (1),88-94 (共著)
45.	2017/07	A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers │ IEICE Transactions on Fundamentals │ E100-A (7),1496-1499 (共著)
46.	2017/07	ILP-based Scheduling for Parallelizable Tasks │ IEICE Transactions on Fundamentals │ E100-A (7),1503-1505 (共著)
47.	2017/07	Static Mapping of Parallelizable Tasks under Deadline Constraints │ IEICE Transactions on Fundamentals │ E100-A (7),1500-1502 (共著)
48.	2017/04	A Dual-Mode Scheduling Approach for Task Graphs with Data Parallelism │ International Journal of Embedded Systems, Inderscience Publishers │ 9 (2),147-156 (共著)
49.	2016/07	Static Mapping of Multiple Parallel Applications on Non-Hierarchical Manycore Embedded Systems │ IEICE Transactions on Fundamentals │ E99-A (7),1417-1419 (共著)
50.	2016/03	Energy-Aware Task Migration for Multiprocessor Real-Time Systems │ Future Generation Computer Systems, Elsevier │ 56,220-228 (共著)
51.	2015/07	高位合成ツールeXCiteで実現する画像フィルタ・システム │ FPGAマガジン, CQ出版 │ (10),44-55 (単著)
52.	2015/06	Function-level Profiling for Embedded Software with QEMU │ International Journal of Embedded Systems, Inderscience Publishers │ 7 (2),170-179 (共著)
53.	2014/12	An Integrated Framework for Energy Optimization of Embedded Real-Time Applications │ IEICE Transactions on Fundamentals │ E97-A (12),2477-2487 (共著)
54.	2014/11	Static Mapping with Dynamic Switching of Multiple Data-Parallel Applications on Embedded Many-core SoCs │ IEICE Transactions on Information and Systems │ E97-D (11),2827-2834 (共著)
55.	2014/07	Novel List Scheduling Strategies for Data Parallelism Task Graphs │ International Journal of Networking and Computing │ 4 (2),279-290 (共著)
56.	2014/03	SEEDS: 組込みシステム向けシステムレベル設計環境 │ 電子情報通信学会論文誌D │ J97-D (3),450-460 (共著)
57.	2014/02	Fast and Accurate Architecture Exploration for High Performance and Low Energy VLIW Data-Path │ IEICE Transactions on Fundamentals │ E97-A (2),606-615 (共著)
58.	2014/02	Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs │ IPSJ Transactions on System LSI Design Methodology │ 7,37-45 (共著)
59.	2013/10	Rainbow: An Operating System for Software-Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs │ International Journal of Reconfigurable Computing │ 2013 (Article ID 789134),40 pages (共著)
60.	2013/10	Static Mapping of Multiple Data-Parallel Applications on Embedded Many-core SoCs │ IEICE Transactions on Information and Systems │ E96-D (10),2268-2271 (共著)
61.	2013/08	Quantitative Evaluation of Resource Sharing in High-Level Synthesis Using Realistic Benchmarks │ IPSJ Transactions on System LSI Design Methodology │ 6,122-126 (共著)
62.	2013/07	Naxim: A Fast and Retargetable Network-on-Chip Simulator with QEMU and SystemC │ International Journal of Networking and Computing │ 3 (2),217-227 (共著)
63.	2013/02	Accurate and Efficient RTL Power Estimation based on Power Contour Model │ Electrical Engineering in Japan │ 182 (3),48-56 (共著)
64.	2012/06	Comparison of Preemption Schemes for Partially Reconfigurable FPGAs │ IEEE Embedded Systems Letters │ 4 (2),45-48 (共著)
65.	2012/02	A Fast Performance Estimation Framework for System-Level Design Space Exploration │ IPSJ Transactions on System LSI Design Methodology │ 5,44-54 (共著)
66.	2012/02	A Novel Framework for Effective Preemptive Hardware Multitasking on FPGAs │ IEICE Transactions on Information and Systems │ E95-D (2),345-353 (共著)
67.	2011/12	実行トレースを用いた組込みシステムにおけるタスク内DVFSのためのチェックポイント抽出 │ 情報処理学会論文誌 │ 52 (12),3729-3744 (共著)
68.	2011/11	等電力曲線モデルに基づく高精度・高効率RTL電力マクロモデル │ 電気学会論文誌C │ 131 (11),1907-1914 (共著)
69.	2011/10	Partitioning and Allocation of Scratch-Pad Memory for Energy Minimization of Priority-Based Preemptive Multi-Task Systems │ IEICE Transactions on Fundamentals │ E94-A (10),1954-1964 (共著)
70.	2011/04	マルチプロセッサ対応システムレベル設計環境 SystemBuilder-MP │ 電子情報通信学会論文誌 │ J94-D (4),657-670 (共著)
71.	2010/12	Automatic Communication Synthesis with Hardware Sharing for Multi-Processor SoC Design │ IEICE Transactions on Fundamentals │ E93-A (12),2509-2516 (共著)
72.	2010/11	オープンソース組込みシステム向けシミュレータのマルチプロセッサ拡張 │ 日本ソフトウェア科学会コンピュータソフトウェア │ 27 (4),24-42 (共著)
73.	2010/10	Static Task Scheduling Algorithms Based on Greedy Heuristics for Battery-Powered DVS Systems │ IEICE Transactions on Information & Systems │ E93-D (10),2737-2746 (共著)
74.	2010/08	Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation │ IPSJ Transactions on System LSI Design Methodology │ 3,179-193 (共著)
75.	2010/02	Partitioning of Behavioral Descriptions Exploiting Function-Level Parallelism │ IEICE Transactions on Fundamentals │ E93-A (2),488-499 (共著)
76.	2009/10	Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-Based High-Level Synthesis │ IPSJ Journal of Information Processing (JIP) │ 17,242-254 (共著)
77.	2009/08	A Generalized Framework for Energy Savings in Hard Real-Time Embedded Systems │ IPSJ Transactions on System LSI Design Methodology │ 2,167-179 (共著)
78.	2009/08	Partitioning and Allocation of Scratch-Pad Memory in Priority-Based Multi-Task Systems │ IPSJ Transactions on System LSI Design Methodology │ 2,180-188 (共著)
79.	2009/07	Effective Scheduling Algorithms for I/O Blocking with a Multi-Frame Task Model │ IEICE Transactions on Information and Systems │ E92-D (7),1412-1420 (共著)
80.	2009/03	動的電圧制御システムにおける評価戦略選択に基づく高効率消費エネルギー関数型プログラミング │ 情報処理学会論文誌プログラミング │ 2 (2),54-69 (共著)
81.	2008/12	Energy Efficiency of Scratch-Pad Memory in Deep Submicron Domains: An Empirical Study │ IEICE Electronics Express │ 5 (23),1010-1016 (共著)
82.	2008/12	High-Level Synthesis of Software Function Calls │ IEICE Transactions on Fundamentals │ E91-A (12),3556-3558 (共著)
83.	2008/10	リアルタイムアプリケーション統合のための柔軟なスケジューリングフレームワーク │ 情報処理学会論文誌 │ 49 (10),3508-3519 (共著)
84.	2008/08	An Effective GA-based Scheduling Algorithm for FlexRay Systems │ IEICE Transactions on Information and Systems │ E91-D (8),2115-2123 (共著)
85.	2008/08	Dynamic Power Management for Embedded System Idle State in the Presence of Periodic Interrupt Services │ IPSJ Transactions on on System LSI Design Methodology │ 1,48-57 (共著)
86.	2008/08	Embedded System Covalidation with RTOS Model and FPGA │ IPSJ Transactions on on System LSI Design Methodology │ 1,126-130 (共著)
87.	2007/12	Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis │ IEICE Transactions on Fundamentals │ E90-A (12),2853-2862 (共著)
88.	2007/09	Function Call Optimization for Efficient Behavioral Synthesis │ IEICE Transactions on Fundamentals │ E90-A (9),2032-2036 (共著)
89.	2007/09	組込みシステムのハードウェア技術 │ システム／制御／情報 │ 51 (9),380-387 (単著)
90.	2007/05	時間保護のためのリアルタイムスケジューリングアルゴリズム │ 情報処理学会論文誌：コンピューティングシステム │ 48 (SIG8 (ACS18)),192-202 (共著)
91.	2007/05	自動車制御分散システムの静的スケジューリング手法 │ 情報処理学会論文誌：コンピューティングシステム │ 48 (SIG8 (ACS18)),203-215 (共著)
92.	2007/01	Practice and Analysis of an Extension Course for Training Trainers of Embedded Software │ ACM SIGBED Review │ 4 (1),73-81 (共著)
93.	2006/09	NEXCESS: 社会人組込みソフトウェア技術者教育におけるスキル育成 │ 工学教育 │ 54 (5),49-54 (共著)
94.	2006/07	社会人に対する組込みソフトウェア技術の再教育の取り組み │ 電気学会論文誌A │ 126 (7),563-569 (共著)
95.	2005/12	動的計画法を用いたキャッシュフラッシュの最悪タイミングの探索手法 │ 情報処理学会論文誌：コンピューティングシステム │ 46 (SIG16 (ACS12)),85-94 (共著)
96.	2005/11	大学における社会人向け組込みソフトウェア技術者人材養成の実施と分析 │ SEC journal │ 1 (4),36-45 (共著)
97.	2005/10	NEXCESS: Nagoya University Extension Courses for Embedded Software Specialists │ ACM SIGBED Review │ 2 (4),20-24 (共著)
98.	2005/09	An RTOS-Based Design and Validation Methodology for Embedded Systems │ IEICE Transactions on Information & Systems │ E88-D (9),2205-2208 (共著)
99.	2005/02	システムレベル設計環境：SystemBuilder │ 電子情報通信学会論文誌D-I │ J88-D-I (2),163-174 (共著)
100.	2004/12	RTOS-Centric Cosimulator for Embedded System Design │ IEICE Transactions on Fundamentals │ E87-A (12),3030-3035 (共著)
101.	2004/10	Impacts of Compiler Optimizations on Address Bus Energy: An Empirical Study │ IEICE Transactions on Fundamentals │ E87-A (10),2815-2820 (単著)
102.	2004/10	オフセット付きCANメッセージの最大遅れ時間解析 │ 情報処理学会論文誌：コンピューティングシステム │ 45 (SIG11 (ACS7)),455-464 (共著)
103.	2004/06	ILP-Based Program Path Analysis for Bounding Worst-Case Inter-Task Cache Conflicts │ IEICE Transactions on Information & Systems │ E87-D (6),1582-1587 (共著)
104.	2004/04	Memory Data Organization for Low-Energy Address Buses │ IEICE Transactions on Electronics │ ,606-612 (共著)
105.	2003/06	Towards Automatic Validation of Dynamic Behavior in Pipelined Processor Specifications │ Kluwer Journal on Design Automation for Embedded Systems │ 8 (2-3),249-265 (共著)
106.	1999/05	組込みシステムの設計技術とその研究 │ 情報処理 │ 40 (5),532-535 (共著)
107.	1998/12	Instruction Scheduling to Reduce Switching Activity of Off-Chip Buses for Low-Power Systems with Caches │ IEICE Transactions on Fundamentals │ E81-A (12),2621-2629 (共著)
108.	1998/12	Language and Compiler for Optimizing Datapath Widths of Embedded Systems │ IEICE Transactions on Fundamentals │ E81-A (12),2595-2604 (共著)
109.	1998/12	Module Selection Using Manufacturing Information │ IEICE Transactions on Fundamentals │ E81-A (12),2576-2584 (共著)
110.	1998/09	Embedded System Design Using Soft-Core Processor and Valen-C │ IIS Journal of Information Science and Engineering │ 14 (3),587-603 (共著)
111.	1998/09	Soft-Core Processor Architecture for Embedded System Design │ IEICE Transactions on Electronics │ E81-C (9),1416-1423 (共著)
112.	1997/10	Code Placement Techniques for Cache Miss Rate Reduction │ ACM Transactions on Design Automation of Electronic Systems (TODAES) │ 2 (4),410-429 (共著)
113.	1997/10	Embedded System Cost Optimization via Data Path Width Adjustment │ IEICE Transactions on Information & Systems │ E80-D (10),974-981 (共著)
114.	1996/10	Satsuki: An Integrated Processor Synthesis and Compiler Generation System │ IEICE Transactions on Information & Systems │ E79-D (10),1373-1381 (共著)
115.	1994/12	アーキテクチャ評価用コンパイラ・ジェネレータの評価 │ 九州大学大学院総合理工学研究科報告 │ 16 (3),339-344 (共著)