Researcher Database

TOMIYAMA Hiroyuki

Department / Course College of Science and Engineering Department of Electronic and Computer Engineering

Title / Position Professor

Papers
1.	2023/11	Empirical Analysis of Power Side-Channel Leakage of High-Level Synthesis Designed AES Circuits │ International Journal of Reconfigurable and Embedded Systems │ 12 (3),pp.305-319 (Co-authored)
2.	2023/05	An Integer Programming Based Approach to Delivery Drone Routing under Load-Dependent Flight Speed │ Drones │ 7 (5) (Co-authored)
3.	2023/03	An Architecture-level Analysis on Deep Learning Models for Low-Impact Computations │ Artificial Intelligence Review │ 56 (3),pp.1971-2010 (Co-authored)
4.	2023/03	Side Channel Power Analysis Resistance Evaluation of Masked Adders on FPGA │ International Journal of Reconfigurable and Embedded Systems │ 12 (1),pp.97-112 (Co-authored)
5.	2023/02	Fast and High-quality Monocular Depth Estimation with Optical Flow for Autonomous Drones │ Drones │ 7 (2) (Co-authored)
6.	2022/11	Shape-Dependent Velocity based Droplet Routing on MEDA Biochips │ IEEE Access │ 10,pp.122423-122430 (Co-authored)
7.	2022/10	ILP-based and Heuristic Scheduling Techniques for Variable-Cycle Approximate Functional Units in High-Level Synthesis │ Computers │ 11 (10) (Co-authored)
8.	2022/06	Optimizing the Deep Neural Networks by Layer-wise Refined Pruning and the Acceleration on FPGA │ Computational Intelligence and Neuroscience │ 2022 (Co-authored)
9.	2022/05	Minimization of MEDA Biochip-Size in Droplet Routing │ Biosensors │ 12 (5) (Co-authored)
10.	2022/04	Mouldable Fork-Join Task Scheduling Techniques with Inter and Intra-Task Communications │ International Journal of Embedded Systems │ 15 (1),pp.69-81 (Co-authored)
11.	2022/03	Pix2Pix-based Monocular Depth Estimation for Drones with Optical Flow on AirSim │ Sensors │ 22 (6) (Co-authored)
12.	2022/03	Simultaneous Scheduling and Core-Type Optimization for Moldable Fork-Join Tasks on Heterogeneous Multicores │ IEICE Transactions on Fundamentals │ E105-A (3),pp.540-548 (Co-authored)
13.	2022/02	Feature Classification-Based Inclination Measurement for Industrial Assembly Platform │ Wireless Communications and Mobile Computing │ 2022 (Co-authored)
14.	2022/02	Load and Wind Aware Routing of Delivery Drones │ Drones │ 6 (2) (Co-authored)
15.	2021/12	A Survey of Convolutional Neural Networks - From Software to Hardware and the Applications in Measurement │ Measurement: Sensors │ 18 (Co-authored)
16.	2021/11	Heuristic Algorithms for Dynamic Scheduling of Moldable Tasks in Multicore Embedded Systems │ International Journal of Reconfigurable and Embedded Systems │ 10 (3),pp.157-167 (Co-authored)
17.	2021/08	Energy-aware Routing of Delivery Drones under Windy Conditions │ IPSJ Transactions on System LSI Design Methodology │ 14,pp.30-39 (Co-authored)
18.	2021/06	A Methodology for Measuring Flight Speed of Drones in Indoor Environments │ Procedia Computer Science │ 187,pp.322-328 (Co-authored)
19.	2021/06	A Skeleton Analysis Based Fall Detection Method Using ToF Camera │ Procedia Computer Science │ 187,pp.252-257 (Co-authored)
20.	2021/06	Pneumonia Diagnosis on Chest X-Rays with Machine Learning │ Procedia Computer Science │ 187,pp.42-51 (Co-authored)
21.	2021/03	A Design Methodology for Approximate Multipliers in Convolutional Neural Networks: A Case of MNIST │ International Journal of Reconfigurable and Embedded Systems │ 10 (1),pp.1-10 (Co-authored)
22.	2021/01	Motion Estimation Based Inclination Measurement of the Assembly Platform │ International Journal of Advanced Mechatronic Systems │ 8 (4),pp.155-165 (Co-authored)
23.	2020/09	A Self-Learning Fall Detection System for Elderly Persons Using Depth Camera │ International Journal of Advanced Mechatronic Systems │ 8 (1),pp.16-25 (Co-authored)
24.	2020/08	A Dynamic Programming Algorithm for Energy-aware Routing of Delivery Drones │ IPSJ Transactions on System LSI Design Methodology │ 13,pp.65-68 (Co-authored)
25.	2020/08	Function-Level Module Sharing Techniques in High-Level Synthesis │ ETRI Journal │ 42 (4),pp.527-533 (Co-authored)
26.	2020/07	A Method of Japanese Ancient Text Recognition by Deep Learning │ Procedia Computer Science, Elsevier │ 174,pp.276-279 (Co-authored)
27.	2020/07	An Edge Computing Based Fall Detection System for Elderly Persons │ Procedia Computer Science, Elsevier │ 174,pp.9-14 (Co-authored)
28.	2020/07	Camera Motion Estimation Algorithm for IoT Devices based on Optimized Feature Tracking Method │ Procedia Computer Science, Elsevier │ 174,pp.22-26 (Co-authored)
29.	2020/07	Machine Learning Based Features Matching for Fatigue Crack Detection │ Procedia Computer Science, Elsevier │ 174,pp.101-105 (Co-authored)
30.	2020/02	A Branch-and-Bound Approach to Scheduling of Data-Parallel Tasks on Multicore Architectures │ International Journal of Embedded Systems, Inderscience Publishers │ 12 (1),pp.125-135 (Co-authored)
31.	2019/12	QoE-Constrained Concurrent Request Optimization Through Collaboration of Edge Servers │ IEEE Internet of Things Journal │ 6 (6),pp.9951-9962 (Co-authored)
32.	2019/10	Energy-Aware Scheduling of Malleable Fork-Join Tasks under a Deadline Constraint on Heterogeneous Multicores │ ACM SIGBED Review │ 16 (3),pp.57-62 (Co-authored)
33.	2019/10	ILP-based Scheduling for Malleable Fork-Join Tasks │ ACM SIGBED Review │ 16 (3),pp.21-26 (Co-authored)
34.	2019/09	Robust Self-Adaptation Fall-Detection System based on Camera Height │ Sensors, MDPI │ 19 (17) (Co-authored)
35.	2019/08	A Genetic Algorithm for Scheduling of Data-Parallel Tasks on Multicore Architectures │ IPSJ Transactions on System LSI Design Methodology │ 12,pp.74-77 (Co-authored)
36.	2019/08	Communication-Aware Scheduling of Data-Parallel Tasks on Multicore Architectures │ IPSJ Transactions on System LSI Design Methodology │ 12,pp.65-73 (Co-authored)
37.	2019/07	A Constraint Programming Approach to Scheduling of Malleable Tasks │ International Journal of Networking and Computing │ 9 (2),pp.131-146 (Co-authored)
38.	2019/02	A HOG-SVM Based Fall Detection IoT System for Elderly Persons Using Deep Sensor │ Procedia Computer Science, Elsevier │ 147,pp.276-282 (Co-authored)
39.	2019/02	An OpenCL-based Software Framework for a Heterogeneous Multicore Architecture on Zynq-7000 SoC │ IPSJ Transactions on System LSI Design Methodology │ 12,pp.46-49 (Co-authored)
40.	2019/02	Design and Evaluation of Asymmetric and Symmetric 32-core Architectures on FPGA │ IPSJ Transactions on System LSI Design Methodology │ 12,pp.42-45 (Co-authored)
41.	2019/02	Three-States-Transition Method for Fall Detection Algorithm Using Depth Image │ Journal of Robotics and Mechatronics │ 31 (1),pp.88-94 (Co-authored)
42.	2017/07	A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers │ IEICE Transactions on Fundamentals │ E100-A (7),pp.1496-1499 (Co-authored)
43.	2017/07	ILP-based Scheduling for Parallelizable Tasks │ IEICE Transactions on Fundamentals │ E100-A (7),pp.1503-1505 (Co-authored)
44.	2017/07	Static Mapping of Parallelizable Tasks under Deadline Constraints │ IEICE Transactions on Fundamentals │ E100-A (7),pp.1500-1502 (Co-authored)
45.	2017/04	A Dual-Mode Scheduling Approach for Task Graphs with Data Parallelism │ International Journal of Embedded Systems, Inderscience Publishers │ 9 (2),pp.147-156 (Co-authored)
46.	2016/07	Static Mapping of Multiple Parallel Applications on Non-Hierarchical Manycore Embedded Systems │ IEICE Transactions on Fundamentals │ E99-A (7),pp.1417-1419 (Co-authored)
47.	2016/03	Energy-Aware Task Migration for Multiprocessor Real-Time Systems │ Future Generation Computer Systems, Elsevier │ 56,pp.220-228 (Co-authored)
48.	2015/06	Function-level Profiling for Embedded Software with QEMU │ International Journal of Embedded Systems, Inderscience Publishers │ 7 (2),pp.170-179 (Co-authored)
49.	2014/12	An Integrated Framework for Energy Optimization of Embedded Real-Time Applications │ IEICE Transactions on Fundamentals │ E97-A (12),pp.2477-2487 (Co-authored)
50.	2014/11	Static Mapping with Dynamic Switching of Multiple Data-Parallel Applications on Embedded Many-core SoCs │ IEICE Transactions on Information and Systems │ E97-D (11),pp.2827-2834 (Co-authored)
51.	2014/07	Novel List Scheduling Strategies for Data Parallelism Task Graphs │ International Journal of Networking and Computing │ 4 (2),pp.279-290 (Co-authored)
52.	2014/03	SEEDS: System-level Design Environment for Embedded Systems │ IEICE Transactions on Information & Systems │ J97-D (3),pp.450-460 (Co-authored)
53.	2014/02	Fast and Accurate Architecture Exploration for High Performance and Low Energy VLIW Data-Path │ IEICE Transactions on Fundamentals │ E97-A (2),pp.606-615 (Co-authored)
54.	2014/02	Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs │ IPSJ Transactions on System LSI Design Methodology │ 7,pp.37-45 (Co-authored)
55.	2013/10	Rainbow: An Operating System for Software-Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs │ International Journal of Reconfigurable Computing │ 2013 (Article ID 789134),pp.40 pages (Co-authored)
56.	2013/10	Static Mapping of Multiple Data-Parallel Applications on Embedded Many-core SoCs │ IEICE Transactions on Information and Systems │ E96-D (10),pp.2268-2271 (Co-authored)
57.	2013/08	Quantitative Evaluation of Resource Sharing in High-Level Synthesis Using Realistic Benchmarks │ IPSJ Transactions on System LSI Design Methodology │ 6,pp.122-126 (Co-authored)
58.	2013/07	Naxim: A Fast and Retargetable Network-on-Chip Simulator with QEMU and SystemC │ International Journal of Networking and Computing │ 3 (2),pp.217-227 (Co-authored)
59.	2013/02	Accurate and Efficient RTL Power Estimation based on Power Contour Model │ Electrical Engineering in Japan │ 182 (3),pp.48-56 (Co-authored)
60.	2012/06	Comparison of Preemption Schemes for Partially Reconfigurable FPGAs │ IEEE Embedded Systems Letters │ 4 (2),pp.45-48 (Co-authored)
61.	2012/02	A Fast Performance Estimation Framework for System-Level Design Space Exploration │ IPSJ Transactions on System LSI Design Methodology │ 5,pp.44-54 (Co-authored)
62.	2012/02	A Novel Framework for Effective Preemptive Hardware Multitasking on FPGAs │ IEICE Transactions on Information and Systems │ E95-D (2),pp.345-353 (Co-authored)
63.	2011/12	Execution Trace Based Checkpoint Extraction for Intra-Task DVFS in Embedded Systems (in Japanese) │ IPSJ Journal │ 52 (12),pp.3729-3744 (Co-authored)
64.	2011/11	An Accurate and Efficient RTL Power Estimation based on Power Contour Model │ IEEJ Transactions on Electronics, Information and Systems │ 131 (11),pp.1907-1914 (Co-authored)
65.	2011/10	Partitioning and Allocation of Scratch-Pad Memory for Energy Minimization of Priority-Based Preemptive Multi-Task Systems │ IEICE Transactions on Fundamentals │ E94-A (10),pp.1954-1964 (Co-authored)
66.	2011/04	SystemBuilder-MP: System-Level Multiprocessor Design Toolset (in Japanese) │ IEICE Transactions on Information and Systems │ J94-D (4),pp.657-670 (Co-authored)
67.	2010/12	Automatic Communication Synthesis with Hardware Sharing for Multi-Processor SoC Design │ IEICE Transactions on Fundamentals │ E93-A (12),pp.2509-2516 (Co-authored)
68.	2010/11	Open Source Simulator for Embedded System Extended Multiprocessor (in Japanese) │ JSSST Computer Software │ 27 (4),pp.24-42 (Co-authored)
69.	2010/10	Static Task Scheduling Algorithms Based on Greedy Heuristics for Battery-Powered DVS Systems │ IEICE Transactions on Information & Systems │ E93-D (10),pp.2737-2746 (Co-authored)
70.	2010/08	Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation │ IPSJ Transactions on System LSI Design Methodology │ 3,pp.179-193 (Co-authored)
71.	2010/02	Partitioning of Behavioral Descriptions Exploiting Function-Level Parallelism │ IEICE Transactions on Fundamentals │ E93-A (2),pp.488-499 (Co-authored)
72.	2009/10	Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-Based High-Level Synthesis │ IPSJ Journal of Information Processing (JIP) │ 17,pp.242-254 (Co-authored)
73.	2009/08	A Generalized Framework for Energy Savings in Hard Real-Time Embedded Systems │ IPSJ Transactions on System LSI Design Methodology │ 2,pp.167-179 (Co-authored)
74.	2009/08	Partitioning and Allocation of Scratch-Pad Memory in Priority-Based Multi-Task Systems │ IPSJ Transactions on System LSI Design Methodology │ 2,pp.180-188 (Co-authored)
75.	2009/07	Effective Scheduling Algorithms for I/O Blocking with a Multi-Frame Task Model │ IEICE Transactions on Information and Systems │ E92-D (7),pp.1412-1420 (Co-authored)
76.	2009/03	Energy Efficient Functional Programing on DVS Systems by Varying Evaluation Strategies (in Japanese) │ IPSJ Transactions on Programming │ 2 (2),pp.54-69 (Co-authored)
77.	2008/12	Energy Efficiency of Scratch-Pad Memory in Deep Submicron Domains: An Empirical Study │ IEICE Electronics Express │ 5 (23),pp.1010-1016 (Co-authored)
78.	2008/12	High-Level Synthesis of Software Function Calls │ IEICE Transactions on Fundamentals │ E91-A (12),pp.3556-3558 (Co-authored)
79.	2008/10	A Flexible Scheduling Framework for Integration of Real-Time Applications (in Japanese) │ IPSJ Journal │ 49 (10),pp.3508-3519 (Co-authored)
80.	2008/08	An Effective GA-based Scheduling Algorithm for FlexRay Systems │ IEICE Transactions on Information and Systems │ E91-D (8),pp.2115-2123 (Co-authored)
81.	2008/08	Dynamic Power Management for Embedded System Idle State in the Presence of Periodic Interrupt Services │ IPSJ Transactions on on System LSI Design Methodology │ 1,pp.48-57 (Co-authored)
82.	2008/08	Embedded System Covalidation with RTOS Model and FPGA │ IPSJ Transactions on on System LSI Design Methodology │ 1,pp.126-130 (Co-authored)
83.	2007/12	Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis │ IEICE Transactions on Fundamentals │ E90-A (12),pp.2853-2862 (Co-authored)
84.	2007/09	Function Call Optimization for Efficient Behavioral Synthesis │ IEICE Transactions on Fundamentals │ E90-A (9),pp.2032-2036 (Co-authored)
85.	2007/09	Hardware Technology for Embedded Systems (in Japanese) │ Systems, Control and Information │ ,pp.380-387 (Sole-authored)
86.	2007/05	Real-Time Scheduling Algorithm for Temporal Protection (in Japanese) │ IPSJ Transactions on Advanced Computing Systems │ 48 (SIG8 (ACS18)),pp.192-202 (Co-authored)
87.	2007/05	A Static Scheduling Method for Distributed Automotive Control Systems (in Japanese) │ IPSJ Transactions on Advanced Computing Systems │ 48 (SIG8 (ACS18)),pp.203-215 (Co-authored)
88.	2007/01	Practice and Analysis of an Extension Course for Training Trainers of Embedded Software │ ACM SIGBED Review │ 4 (1),pp.73-81 (Co-authored)
89.	2006/09	NEXCESS: Education for Embedded Software Specialists - Enhance Worker’s Skill (in Japanese) │ Journal of JSEE │ 54 (5),pp.49-54 (Co-authored)
90.	2006/07	Remedial Education of Embedded Software Specialists for Working People (in Japanese) │ IEEJ Transactions on Fundamentals and Materials, vol. 126-A, no. 7 │ 126 (7),pp.563-569 (Co-authored)
91.	2005/12	A Search Algorithm of Worst-Case Cache Flush Timings Using Dynamic Programming (in Japanese) │ IPSJ Transactions on Advanced Computing Systems │ 46 (SIG16 (ACS12)),pp.85-94 (Co-authored)
92.	2005/11	Practice and Analysis of Extension Courses for Embedded Software Specialists in a University (in Japanese) │ SEC journal │ 1 (4),pp.36-45 (Co-authored)
93.	2005/10	NEXCESS: Nagoya University Extension Courses for Embedded Software Specialists │ ACM SIGBED Review │ 2 (4),pp.20-24 (Co-authored)
94.	2005/09	An RTOS-Based Design and Validation Methodology for Embedded Systems │ IEICE Transactions on Information & Systems │ E88-D (9),pp.2205-2208 (Co-authored)
95.	2005/02	SystemBuilder: A System Level Design Environment (in Japanese) │ IEICE Transactions on Information & Systems │ J88-D-I (2),pp.163-174 (Co-authored)
96.	2004/12	RTOS-Centric Cosimulator for Embedded System Design │ IEICE Transactions on Fundamentals │ E87-A (12),pp.3030-3035 (Co-authored)
97.	2004/10	Impacts of Compiler Optimizations on Address Bus Energy: An Empirical Study │ IEICE Transactions on Fundamentals │ E87-A (10),pp.2815-2820 (Sole-authored)
98.	2004/10	Response Time Analysis for Grouped CAN Messages with Offsets (in Japanese) │ IPSJ Transactions on Advanced Computing Systems │ 45 (SIG11 (ACS7)),pp.455-464 (Co-authored)
99.	2004/06	ILP-Based Program Path Analysis for Bounding Worst-Case Inter-Task Cache Conflicts │ IEICE Transactions on Information & Systems │ E87-D (6),pp.1582-1587 (Co-authored)
100.	2004/04	Memory Data Organization for Low-Energy Address Buses │ IEICE Transactions on Electronics │ ,pp.606-612 (Co-authored)
101.	2003/06	Towards Automatic Validation of Dynamic Behavior in Pipelined Processor Specifications │ Kluwer Journal on Design Automation for Embedded Systems │ 8 (2-3),pp.249-265 (Co-authored)
102.	1999/05	Design Technology of Embedded Systems and Its Research Trends (in Japanese) │ IPSJ Magazine │ 40 (5),pp.532-535 (Co-authored)
103.	1998/12	Instruction Scheduling to Reduce Switching Activity of Off-Chip Buses for Low-Power Systems with Caches │ IEICE Transactions on Fundamentals │ E81-A (12),pp.2621-2629 (Co-authored)
104.	1998/12	Language and Compiler for Optimizing Datapath Widths of Embedded Systems │ IEICE Transactions on Fundamentals │ E81-A (12),pp.2595-2604 (Co-authored)
105.	1998/12	Module Selection Using Manufacturing Information │ IEICE Transactions on Fundamentals │ E81-A (12),pp.2576-2584 (Co-authored)
106.	1998/09	Embedded System Design Using Soft-Core Processor and Valen-C │ IIS Journal of Information Science and Engineering │ 14 (3),pp.587-603 (Co-authored)
107.	1998/09	Soft-Core Processor Architecture for Embedded System Design │ IEICE Transactions on Electronics │ E81-C (9),pp.1416-1423 (Co-authored)
108.	1997/10	Code Placement Techniques for Cache Miss Rate Reduction │ ACM Transactions on Design Automation of Electronic Systems (TODAES) │ 2 (4),pp.410-429 (Co-authored)
109.	1997/10	Embedded System Cost Optimization via Data Path Width Adjustment │ IEICE Transactions on Information & Systems │ E80-D (10),pp.974-981 (Co-authored)
110.	1996/10	Satsuki: An Integrated Processor Synthesis and Compiler Generation System │ IEICE Transactions on Information & Systems │ E79-D (10),pp.1373-1381 (Co-authored)
111.	1994/12	Evaluation of Compiler Generator for Computer Architecture Evaluation (in Japanese) │ Engineering Sciences Reports, Kyushu University │ 16 (3),pp.339-344 (Co-authored)