研究者学術情報データベース

トミヤマ　ヒロユキ
冨山　宏之
TOMIYAMA Hiroyuki

所属理工学部電子情報工学科

職名教授

学会発表
1.	2023/06	A Deep Reinforcement Learning-Based Routing Algorithm for Unknown Erroneous Cells in DMFBs (Interregional NEWCAS Conference (Accepted))
2.	2023/06	A Fast Approach to Droplet Routing with Shape-Dependent Velocity on MEDA Biochips (Interregional NEWCAS Conference (Accepted))
3.	2023/02	Empirical Analysis of Side-Channel Attack Resistance of HLS-Designed AES Circuits (International Conference on Electronics, Information, and Communication (ICEIC))
4.	2023/02	Impacts of Clock Constraints on Side-Channel Leakage of HLS-Designed AES Circuits (International Conference on Electronics, Information, and Communication (ICEIC))
5.	2023/02	Multi-Droplet Routing Based on a Shape-Dependent Velocity Model on MEDA Biochips (International Conference on Electronics, Information, and Communication (ICEIC))
6.	2023/01	Transport-Free Placement of Mixers for Realizing Bioprotocol on Programmable Microfluidic Devices (International Conference on VLSI Design)
7.	2022/11	Energy Consumption Reduction through Resource Allocation Using Docker (In Proc. of International Workshop on Advances in Networking and Computing (WANC) in conjunction with International Symposium on Computing and Networking (CANDAR), pp. 436-437)
8.	2022/10	Binding and Scheduling of 2×3 Mixers for Transport-Free Sample Preparation Using Programmable Microfluidic Devices (In Proc. of Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 32-37)
9.	2022/10	Full Hardware Implementation of RTOS-Based Systems Using General High-Level Synthesizer (In Proc. of Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 2-7)
10.	2022/10	Fusing Infrared and Visible Images for DNN-based Nighttime Human Detection (In Proc. of International SoC Design Conference (ISOCC), pp. 203-204)
11.	2022/10	Monocular Depth Estimation with Optical Flow Attention for Autonomous Drones (In Proc. of International SoC Design Conference (ISOCC), pp. 197-198)
12.	2022/08	A Case Study on Forehand Footwork Mistake Detection in Table Tennis (In Proc. of International Symposium on Advanced Technologies and Applications in the Internet of Things (ATAIT), pp. 7-16,)
13.	2022/08	A Heuristic Scheduling Algorithm with Variable Cycle Approximate Functional Units in High Level Synthesis (In Proc. of International Symposium on Advanced Technologies and Applications in the Internet of Things (ATAIT), pp. 53-59)
14.	2022/08	An Accuracy Controllable Approximate Adder for FPGAs (In Proc. of International Symposium on Advanced Technologies and Applications in the Internet of Things (ATAIT), pp. 60-66)
15.	2022/08	Delivery Drone Routing under Load dependent Flight Speed based on Integer Quadratic Programming (In Proc. of International Symposium on Advanced Technologies and Applications in the Internet of Things (ATAIT), pp. 35-42)
16.	2022/08	Evaluation of Power Analysis Attack Resistance of Masked Adders on FPGA (In Proc. of International Symposium on Advanced Technologies and Applications in the Internet of Things (ATAIT), pp. 67-74)
17.	2022/08	Monocular Thermal Camera Depth Estimation with Optical Flow for Autonomous Drones (In Proc. of International Symposium on Advanced Technologies and Applications in the Internet of Things (ATAIT), pp. 43-52)
18.	2022/06	A Fair-Policy Dynamic Scheduling Algorithm for Moldable Gang Tasks on Multicores (Proc. of Mediterranean Conference on Embedded Computing (MECO), pp. 172-175)
19.	2022/06	Container-based Throughput Balancing for Multiple Streaming Applications: A Case Study (In Proc. of Mediterranean Conference on Embedded Computing (MECO), pp. 199-202)
20.	2022/02	An ILP-based Approach to Delivery Drone Routing under Load-dependent Flight Speed (International Conference on Electronics, Information, and Communication (ICEIC))
21.	2022/02	Depth Estimation from Monocular Infrared Images for Autonomous Flight of Drones (International Conference on Electronics, Information, and Communication (ICEIC))
22.	2022/02	Priority-aware Static Task Mapping for Edge-Cloud Platforms (International Conference on Electronics, Information, and Communication (ICEIC))
23.	2021/10	Design of a 32-bit Accuracy-Controllable Approximate Multiplier for FPGAs (International SoC Design Conference (ISOCC))
24.	2021/10	High-Level Synthesis of Approximate Computing Circuits with Dual Accuracy Modes (International SoC Design Conference (ISOCC))
25.	2021/10	Impacts of HLS Optimizations on Side-Channel Leakage for AES Circuits (International SoC Design Conference (ISOCC))
26.	2021/10	Minimization of Routing Area in MEDA Biochips (Biomedical Circuits and Systems Conference (BioCAS))
27.	2021/10	Power Side-Channel Analysis for Different Adders on FPGA (International SoC Design Conference (ISOCC))
28.	2021/10	Scheduling with Variable-Cycle Approximate Functional Units in High-Level Synthesis (International SoC Design Conference (ISOCC))
29.	2021/08/24	Frailty Classification Based on Artificial Intelligence (In Proc. of International Symposium on Advanced Technologies and Applications in the Internet of Things (ATAIT), pp. 99-107)
30.	2021/08/24	Pix2Pix-Based Depth Estimation from Monocular Images for Dynamic Path Planning of Multirotor on AirSim (In Proc. of International Symposium on Advanced Technologies and Applications in the Internet of Things (ATAIT), pp. 1-9)
31.	2021/08/24	Routing of Delivery Drones Considering Load and Wind Effects (In Proc. of International Symposium on Advanced Technologies and Applications in the Internet of Things (ATAIT), pp. 116-125)
32.	2021/08	A Survey of Convolutional Neural Networks - From Software to Hardware and the Applications in Measurement (International Measurement Confederation (IMEKO))
33.	2021/06/24	A Comprehensive Analysis of Low-Impact Computations in Deep Learning Workloads (Proc. of Great Lakes Symposium on VLSI (GLSVLSI), pp. 385-390)
34.	2021/04/14	A Toolkit for Power Behavior Analysis of HLS-Designed FPGA Circuits (In Proc. of Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips))
35.	2021/03/29	Improved Modeling of Energy Consumption of Delivery Drones (In Proc. of Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 56-60)
36.	2021/03/02	A Dynamic Path Planning Method for Multirotor Using Depth Images in AirSim (In Proc. of International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP), pp. 341-344)
37.	2021/03/02	A Low-power Security Camera System Using OpenCV and YOLO (In Proc. of International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP), pp. 298-300)
38.	2021/03/02	Improvement of Detection Rate Using Preprocessed Infrared Images (In Proc. of International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP), pp. 337-340)
39.	2021/03/01	Accuracy and Speed Evaluation of Eye Blink Detection Algorithms via OpenCV and Dlib Libraries (In Proc. of International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP), pp. 57-60)
40.	2021/02/02	A Home Security Camera System with Container-based Resource Allocation on Raspberry Pi (In Proc. of International Conference on Electronics, Information, and Communication (ICEIC))
41.	2020/12/12	Rubbing Character Recognition with Machine Learning (Proc. of International Conference on Advanced Mechatronic Systems (ICAMechS), pp. 290-295)
42.	2020/11/28	A Methodology for Measuring Flight Speed of Drones in Indoor Environments (International Conference on Identification, Information and Knowledge in the Internet of Things (IIKI))
43.	2020/11/28	A Skeleton Analysis Based Fall Detection Method Using ToF Camera (International Conference on Identification, Information and Knowledge in the Internet of Things (IIKI))
44.	2020/11/28	Pneumonia Diagnosis on Chest X-Rays with Machine Learning (International Conference on Identification, Information and Knowledge in the Internet of Things (IIKI))
45.	2020/10/23	A Case Study on Rubbing Character Recognition Based on Deep Learning (International SoC Design Conference (ISOCC), pp. 318-319)
46.	2020/10/23	A Quadcopters Flight Simulation Considering the Influence of Wind (International SoC Design Conference (ISOCC), pp. 334-335)
47.	2020/10/23	An Evaluation of Edge Computing Platform for Reliable Automated Drones (International SoC Design Conference (ISOCC), pp. 95-96)
48.	2020/10/23	Scheduling of Rigid Tasks on Heterogeneous Multicores (International SoC Design Conference (ISOCC), pp. 330-331)
49.	2020/10/22	Heuristic Algorithms for Dynamic Scheduling of Moldable Tasks (International SoC Design Conference (ISOCC), pp. 55-56)
50.	2020/05/25	Scheduling of Moldable Fork-Join Tasks with Inter- and Intra-Task Communications (In Proc. of International Workshop on Software and Compilers for Embedded Systems (SCOPES), pp. 7-12)
51.	2020/02/24	Frame Detection and Text Line Segmentation for Early Japanese Books Understanding (In Proc. of International Conference on Pattern Recognition Applications and Methods (ICPRAM), pp. 600-606)
52.	2019/12/04	Work-in-Progress: Routing of Delivery Drones with Load-Dependent Flight Speed (In Proc. of Real-Time Systems Symposium (RTSS), pp. 520-523)
53.	2019/11/29	Evaluation of the RuCL Framework on Raspberry Pi (International Workshop on Networking, Computing, Systems, and Software (NCSS) in conjunction with International Symposium on Computing and Networking (CANDAR))
54.	2019/11/29	Measurement of Performance and Energy Consumption of OpenCV Programs on Raspberry Pi (International Workshop on Networking, Computing, Systems, and Software (NCSS) in conjunction with International Symposium on Computing and Networking (CANDAR))
55.	2019/11/27	A Web-based Routing and Visualization Tool for Drone Delivery (In Proc. of Sustainable Computing Systems Workshop (SUSCW) in conjunction with International Symposium on Computing and Networking (CANDAR), pp. 264-268)
56.	2019/10/26	A Method of Japanese Ancient Text Recognition by Deep Learning (International Conference on Identification, Information and Knowledge in the Internet of Things (IIKI))
57.	2019/10/26	An Edge Computing Based Fall Detection System for Elderly Persons (International Conference on Identification, Information and Knowledge in the Internet of Things (IIKI))
58.	2019/10/26	Comparison Works Regarding Camera Motion Estimation Approaches Intended for IoT Devices (International Conference on Identification, Information and Knowledge in the Internet of Things (IIKI))
59.	2019/10/26	Machine Learning Based Features Matching for Fatigue Crack Detection (International Conference on Identification, Information and Knowledge in the Internet of Things (IIKI))
60.	2019/10/22	A Case Study on Design of Approximate Multipliers for MNIST CNN (In Proc. of Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 251-255)
61.	2019/10/07	Function-Level Module Sharing in High-Level Synthesis (In Proc. of International SoC Design Conference (ISOCC), pp. 50-51)
62.	2019/10/07	Lucas-Kanade Optical Flow Based Camera Motion Estimation Approach (In Proc. of International SoC Design Conference (ISOCC), pp. 77-78)
63.	2019/10/07	Maximum Error-Aware Design of Approximate Array Multipliers (In Proc. of International SoC Design Conference (ISOCC), pp. 73-74)
64.	2019/10/07	Scheduling of Malleable Tasks with DMA-based Communication (In Proc. of International SoC Design Conference (ISOCC), pp. 48-49)
65.	2019/08/30	Deep Learning based Japanese Early Books Understanding (In Proc. of Conference of Japanese Association for Digital Humanities (JADH), pp. 84-85)
66.	2019/08/30	Rubbing Character Recognition base on Deep Learning and Lexical Analysis (In Proc. of Conference of Japanese Association for Digital Humanities (JADH), pp. 113-115)
67.	2019/08/28	Camera Motion Estimation and Optimization Approach (In Proc. of International Conference on Advanced Mechatronic Systems (ICAMechS), pp. 212-217)
68.	2019/08/28	Gender Classification of Elderly People using Doppler Radar Images based on Machine Learning (In Proc. of International Conference on Advanced Mechatronic Systems (ICAMechS), pp. 305-310)
69.	2019/08/28	The Early Japanese Books Text Line Segmentation base on Image Processing and Deep Learning (In Proc. of International Conference on Advanced Mechatronic Systems (ICAMechS), pp. 299-304)
70.	2019/08/27	A Dynamic Height Analysis on Vision Based Fall Detection System (In Proc. of International Conference on Advanced Mechatronic Systems (ICAMechS), pp. 148-151)
71.	2019/08/27	Deep Learning and Lexical Analysis Combined Rubbing Character Recognition (In Proc. of International Conference on Advanced Mechatronic Systems (ICAMechS), pp. 57-62)
72.	2019/08/27	Multiple States Fall Detection System for Senior Citizens (In Proc. of International Conference on Advanced Mechatronic Systems (ICAMechS), pp. 169-174)
73.	2019/07/09	Static Scheduling of Parallel Tasks (International Forum on MPSoC for Software-defined Hardware (MPSoC))
74.	2019/05/24	A Dynamic Programming Algorithm for Energy-aware Routing of Delivery Drones (International Conference on Artificial Intelligence and Data Engineering (AIDE))
75.	2019/05/24	A Home Security Camera System based on Cloud and SNS (International Conference on Artificial Intelligence and Data Engineering (AIDE))
76.	2019/05/24	Stereo Vision based Depth Estimation (International Conference on Artificial Intelligence and Data Engineering (AIDE))
77.	2019/05/23	A Neck-floor Distance Analysis Based Fall Detection System Using Deep Camera (International Conference on Artificial Intelligence and Data Engineering (AIDE))
78.	2019/01/28	Communication-Aware Scheduling for Malleable Tasks (In Proc. of International Conference on Platform Technology and Service (PlatCon), pp. 11-16)
79.	2018/11/29	Revisiting Thread Execution Methods for GPU-oriented OpenCL Programs on Multicore Processors (In Proc. of International Workshop on Advances in Networking and Computing (WANC) in conjunction with International Symposium on Computing and Networking (CANDAR), pp. 520-523)
80.	2018/11/29	Scheduling of Malleable Fork-Join Tasks with Constraint Programming (In Proc. of International Symposium on Computing and Networking (CANDAR), pp. 133-138)
81.	2018/11/28	A Case Study on Memory Architecture Exploration for Manycores on an FPGA (In Proc. of International Workshop on Computer Systems and Architectures (CSA) in conjunction with International Symposium on Computing and Networking (CANDAR), pp. 132-137)
82.	2018/11/28	Low-Energy Routing for Deadline-constrained Delivery Drones under Windy Conditions (International Workshop on Networking, Computing, Systems, and Software (NCSS) in conjunction with International Symposium on Computing and Networking (CANDAR))
83.	2018/11/26	An Ocean Target Detection Mechanism in IoT Environment (Internet Conference (IC))
84.	2018/10/30	Scheduling of Malleable Tasks Based on Constraint Programming (In Proc. of IEEE Region 10 Conference (TENCON), pp. 1499-1504)
85.	2018/10/20	A HOG-SVM Based Fall Detection IoT System for Elderly Persons Using Deep Sensor (In Proc. of International Conference on Identification, Information and Knowledge in the Internet of Things (IIKI))
86.	2018/10/04	Energy-Aware Scheduling of Malleable Fork-Join Tasks under a Deadline Constraint on Heterogeneous Multicores (In Proc. of Embedded Operating System Workshop (EWiLi))
87.	2018/10/04	Synthesis of Full Hardware Implementation of RTOS-Based Systems (In Proc. of International Symposium on Rapid System Prototyping (RSP), pp. 1-7)
88.	2018/10/03	Work-in-Progress: Communication-Aware Scheduling of Data-Parallel Tasks (In Proc. of International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES))
89.	2018/09/01	Distance Measurement and Camera Calibration based on Binocular Vision Technology (In Proc. of International Conference on Advanced Mechatronic Systems (ICAMechS), pp. 349-354)
90.	2018/08/31	A Privacy Protected Fall Detection IoT System for Elderly Persons using Depth Camera (In Proc. of International Conference on Advanced Mechatronic Systems (ICAMechS), pp. 31-35)
91.	2018/08/03	A Systematic Approach to Design of Approximate Array Multipliers (Taiwan and Japan Conference on Circuits and Systems (TJCAS))
92.	2018/08/03	Function-Level Module Sharing with High-Level Synthesis (Taiwan and Japan Conference on Circuits and Systems (TJCAS))
93.	2018/08/03	High-Level Synthesis of the CHStone Benchmark Programs with SDSoC (Taiwan and Japan Conference on Circuits and Systems (TJCAS))
94.	2018/08/02	A Danger Detection IoT System for Elderly Persons (Taiwan and Japan Conference on Circuits and Systems (TJCAS))
95.	2018/08/02	A Security Camera System with Cloud and SNS (Taiwan and Japan Conference on Circuits and Systems (TJCAS))
96.	2018/08/02	Distance Measurement for Pose Estimation based on Binocular Vision Technology (Taiwan and Japan Conference on Circuits and Systems (TJCAS))
97.	2018/08/02	Protecting Lake Environment using Underwater-drone and Deep Learning (Taiwan and Japan Conference on Circuits and Systems (TJCAS))
98.	2018/04/13	A Genetic Algorithm for Scheduling of Data-Parallel Tasks (International Symposium on Advanced Technologies and Applications in the Internet of Things (ATAIT))
99.	2018/04/13	A Heterogeneous Multicore Architecture and a Parallel Software Environment for Zynq SoC (International Symposium on Advanced Technologies and Applications in the Internet of Things (ATAIT))
100.	2018/04/13	A Kinect-based Stand-to-fall Analysis for Elderly People (International Symposium on Advanced Technologies and Applications in the Internet of Things (ATAIT))
101.	2018/04/13	Coordinate Transformations for Binocular Vision Systems (International Symposium on Advanced Technologies and Applications in the Internet of Things (ATAIT))
102.	2018/04/13	Design of Asymmetric and Symmetric 32-core Architectures on FPGA (International Symposium on Advanced Technologies and Applications in the Internet of Things (ATAIT))
103.	2018/03/26	Measurement and Modeling of Quadcopter Energy with ROS (In Proc of Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 169-173)
104.	2017/12/08	Fall Detection for Elderly Persons Using a Depth Camera (Proc. of International Conference on Advanced Mechatronic Systems (ICAMechS), pp. 269-273)
105.	2017/11/20	Power Measurement and Modeling of Quadcopters on Horizontal Flight (International Workshop on Computer Systems and Architectures (CSA) in conjunction with International Symposium on Computing and Networking (CANDAR), pp. 326-329)
106.	2017/10/20	Binary Synthesis Implementing External Interrupt Handler as Independent Module (In Proc. of International Symposium on Rapid System Prototyping (RSP), pp. 92-98)
107.	2017/10/20	Systematic Design of Approximate Array Multipliers with Different Accuracy (International Workshop on Highly Efficient Neural Networks Design (HENND) in conjunction with ESWEEK)
108.	2017/08/23	A Study on Window Sizes in NLM Filter (Taiwan and Japan Conference on Circuits and Systems (TJCAS), p. 71)
109.	2016/10/27	A Systematic Methodology for Design and Analysis of Approximate Array Multipliers (In Proc. of Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 352-354)
110.	2016/10/24	A Branch-and-Bound Algorithm for Scheduling of Data-Parallel Tasks (In Proc. of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 96-100)
111.	2016/08/01	An Internet-of-Things Simulation Framework with QEMU (Taiwan and Japan Conference on Circuits and Systems (TJCAS))
112.	2016/08/01	Analysis of Hierarchical 32-Core Architectures for FPGA-based Embedded Systems (Taiwan and Japan Conference on Circuits and Systems (TJCAS))
113.	2016/07/15	Energy Modeling and Optimization for Delivery Quadcopters (International Forum on MPSoC for Software-defined Hardware (MPSoC))
114.	2016/07/12	An OpenCL Framework for FPGA-based Heterogeneous Multicore Architecture (In Proc. of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), pp. 443-444)
115.	2016/07/12	Fundamental Analysis of Low Energy Path Routing for Delivery Quadcopters (In Proc. of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), pp. 595-596)
116.	2016/07/12	ILP-based Scheduling for Malleable Parallel Tasks (In Proc. of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), pp. 445-446)
117.	2016/07/11	Deadline-Constrained Static Mapping of Parallelizable Tasks on Manycore Architectures (In Proc. of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), pp. 33-36)
118.	2016/04	A Case Study on Exploration of FPGA-based Multicore/Manycore Architectures (In Proc. of International Symposium on Low-Power and High-Speed Chips (COOL Chips))
119.	2015/10	Comparison of Thread Execution Methods for GPU-oriented OpenCL Programs on Multicore Processors (In Proc. of Embedded Operating Systems Workshop (EWiLi))
120.	2015/07	PUF-based Security Enhancement for Automotive Software Update (International Forum on MPSoC for Software-defined Hardware (MPSoC))
121.	2015/06	A Flexible Simulation Framework for Network-on-Chip with QEMU and SystemC (In Proc. of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), pp. 661-663)
122.	2015/06	A Lightweight OpenCL Framework for Embedded Multicore Processors (In Proc. of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), pp. 355-357)
123.	2015/06	Design and Implementation of Hierarchical 32-Core Architecture for FPGA-based Embedded Systems (In Proc. of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), pp. 346-348)
124.	2015/06	Efficient Execution of OpenCL-based GPU Programs on Multicore Processors (In Proc. of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), pp. 352-354)
125.	2015/06	Revisiting Function Inlining in FPGA High-Level Synthesis (In Proc. of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), pp. 349-351)
126.	2015/06	Static Task Mapping for Non-Hierarchical Manycore SoCs (In Proc. of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), pp. 519-521)
127.	2015/03	High-Level Synthesis from Programs with External Interrupt Handling (In Proc. of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 10-15)
128.	2015/03	Profiling-Driven Multi-Cycling in FPGA High-Level Synthesis (In Proc. of Design, Automation & Test in Europe (DATE), pp. 31-36)
129.	2014/11	A Dual-Mode Scheduling Algorithm for Task Graphs with Data Parallelism (In Proc. of Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 371-374)
130.	2014/08	Cache Simulation for Instruction Set Simulator QEMU (In Proc. of International Workshop on Software Defined Sensor Networks (SDSN), World Ubiquitous Science Congress (U-Science), pp. 441-446)
131.	2014/08	Task Migration for Energy Saving in Real-Time Multiprocessor Systems (In Proc. of International Conference on Embedded Software and Systems (ICESS), pp. 693-700)
132.	2014/07	ACAP: Binary Synthesizer Based on MIPS Object Codes (In Proc. of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Invited paper, pp. 725-728)
133.	2014/07	Yield-Aware Allocation and Binding of Partially-Programmable Functional Units (In Proc. of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Invited paper, pp. 729-732)
134.	2014/05	Fast Design-Space Exploration Method for SW/HW Codesign on FPGAs (In Proc. of International Symposium on Field-Programmable Custom Computing Machines (FCCM), Poster, p. 235)
135.	2013/12	List Scheduling Strategies for Task Graphs with Data Parallelism (In Proc. of International Symposium on Computing and Networking (CANDAR), pp. 168-172)
136.	2013/11	A Basic-Block Level Optimistic Energy Estimation for Power-Gated VLIW Data-Path Model (In Proc. of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 354-359)
137.	2013/11	A Hardware/Software Cosimulator for Network-on-Chip (In Proc. of International SoC Design Conference (ISOCC), pp. 172-175)
138.	2013/09	A New Metric for Basic-Block Level Rough Energy Estimation for Power-Gated VLIW Data-Path Model (In Proc. of International Symposium on Communications and Information Technologies (ISCIT), pp. 320-324)
139.	2013/09	A Static Task Mapping Algorithm with Dynamic Task Switching for Embedded Many-core SoCs (In Proc. of International Symposium on Communications and Information Technologies (ISCIT), pp. 293-297)
140.	2013/09	Design, Implementation and Evaluation of Built-in Functions on Parallel Programming Model in SMYLE OpenCL (In Proc. of International Symposium on Embedded Multicore SoCs (MCSoC), pp. 113-118)
141.	2013/09	GA-based Architecture Exploration Method for Low Energy VLIW Data-Path Model (In Proc. of International Symposium on Communications and Information Technologies (ISCIT), pp. 307-310)
142.	2013/09	SMYLE OpenCL: A Parallel Programming Framework for Embedded Manycore SoCs (SNU-ESRC and Samsung-SATTI Joint Workshop)
143.	2013/08	Function Profiling for Embedded Software by Utilizing QEMU and Analyzer Tool (In Proc. of International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1251-1254)
144.	2013/07	Simulation of Many-core NoCs with QEMU and SystemC (International Forum on Embedded MPSoC and Multicore (MPSoC))
145.	2013/06	Automated Identification of Performance Bottleneck on Embedded Systems for Design Space Exploration (In Proc. of International Embedded Systems Symposium (IESS), Springer IFIP 403, pp. 171-180)
146.	2013/05	Partial Contoller Retiming in High-Level Synthesis (In Proc. of Electronic System Level Synthesis Conference (ESLsyn), pp. 10-15)
147.	2013/03	Cost-Efficient Scheduling in High-Level Synthesis for Soft-Error Vulnerability Mitigation (Iin Proc. of International Symposium on Quality Electronic Design (ISQED), pp. 518-523)
148.	2013/01	SMYLE OpenCL: A Programming Framework for Embedded Many-Core SoCs (In Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC), Invited paper, pp. 565-567)
149.	2012/12	A Fast Network-on-Chip Simulator with QEMU and SystemC (In Proc. of International Workshop on Advances in Networking and Computing (WANC) in conjunction with International Conference on Networking and Computing (ICNC), pp. 298-301)
150.	2012/11	Energy-Aware ILP-based Instruction Scheduling for Fine-Grained Power-Gated VLIW Processors (In Proc. of International SoC Design Conference (ISOCC), pp. 139-142)
151.	2012/11	Task Mapping Techniques for Embedded Many-core SoCs (In Proc. of International SoC Design Conference (ISOCC), pp. 204-207)
152.	2012/07	OpenCL Compiler and Runtime Library for Embedded Manycore SoCs (International Forum on Embedded MPSoC and Multicore (MPSoC))
153.	2012/06	Selective Resource Sharing with RT-Level Retiming for Clock Enhancement in High-Level Synthesis (In Proc. of International Conference on Embedded Software and Systems (ICESS), pp. 1534-1540)
154.	2012/03	An NoC Virtual Platform Based on QEMU and SystemC (Poster Presentation at Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications (DEPCP) in conjunction with Design Automation and Test in Europe (DATE))
155.	2012/03	An OpenCL Implementation Supporting Task Parallel Execution on Embedded Many-core Architecture (Poster Presentation at Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications (DEPCP) in conjunction with Design Automation and Test in Europe (DATE))
156.	2012/03	High-Level Synthesis Using Partially-Programmable Resources for Yield Improvement (In Proc. of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 414-419)
157.	2012/01	Clock-Constrained Simultaneous Allocation and Binding for Multiplexer Optimization in High-Level Synthesis (In Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 251-256)
158.	2011/11	Fast Design Space Exploration for Mixed Hardware-Software Embedded Systems (In Proc. of International SoC Design Conference (ISOCC), pp. 92-95)
159.	2011/11	Hardware Multitasking in Dynamically Partially Reconfigurable FPGA-based Embedded Systems (In Proc. of International SoC Design Conference (ISOCC), Invited paper, pp. 183-186)
160.	2011/11	Rainbow - An OS Extension for Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs (In Proc. of International Conference on ReConFigurable Computing and FPGAs (ReConFig), pp. 416-421)
161.	2011/08	An Energy Aware Design Space Exploration for VLIW AGU Model with Fine Grained Power Gating (In Proc. of Euromicro Conference on Digital System Design (DSD), pp. 693-700)
162.	2011/08	An Integrated Optimization Framework for Reducing the Energy Consumption of Embedded Real-Time Applications (Proc. of International Symposium on Low-Power Electronics and Design (ISLPED), pp. 271-276)
163.	2011/07	Challenges of Programming Embedded Many-Core SoCs with OpenCL (International Forum on Embedded MPSoC and Multicore (MPSoC))
164.	2011/06	Architecture Optimization based on a Branch-and-Bound Strategy for Low-Energy Embedded VLIW Processors (Proc. of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), pp. 207-210)
165.	2011/06	Energy-Aware ILP-based Instruction Scheduling for Fine-Grained Power-Gated VLIW Processors (Proc. of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), pp. 211-214)
166.	2011/01	Checkpoints Extraction Using Execution Traces for Intra-Task DVFS in Embedded Systems (Proc. of International Symposium on Electronic Design, Test and Applications (DELTA), pp. 19-24)
167.	2010/11	Advanced SystemBuilder: A Tool Set for Multiprocessor Design Space Exploration (Proc. of International SoC Design Conference (ISOCC), Invited paper, pp. 79-82)
168.	2010/11	Towards Practical High-Level Synthesis From Large Behavioral Descriptions (Proc. of International SoC Design Conference (ISOCC), Invited paper, pp. 71-74)
169.	2010/10	Aggressive Register Unsharing with Selective FU Sharing in High-Level Synthesis (Proc. of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 13-18)
170.	2010/10	Efficient Utilization of Scratch-Pad Memory in Preemptive Multi-Task Systems (Workshop on Compiler-Assisted System-On-Chip Assembly (CASA) in conjunction with Embedded Systems Week (ESWEEK))
171.	2010/10	Minimizing Inter-Task Interferences in Scratch-Pad Memory Usage for Reducing the Energy Consumption of Multi-Task Systems (Proc. of International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), pp. 157-166)
172.	2010/10	Placing Static and Stack Data into a Scratch-Pad Memory for Reducing the Energy Consumption of Multi-task Applications (Proc. of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), Outstanding Paper Award, pp. 7-12)
173.	2010/08	A Novel Mechanism for Effective Hardware Task Preemption in Dynamically Reconfigurable Systems (Proc. of International Conference on Field Programmable Logic and Applications (FPL), pp. 352-355)
174.	2010/05	Automatic Communication Synthesis with Hardware Sharing for Design Space Exploration (Proc. of International Symposium on Circuits and Systems (ISCAS), pp. 1863-1866)
175.	2010/03	Partitioning and Allocation of Scratch-Pad Memory for Priority-Based Preemptive Multi-Task Systems (Proc. of Design Automation and Test in Europe (DATE), pp. 1124-1129)
176.	2010/01	Aggressive Register Unsharing Based on SSA Transformation for Clock Enhancement in High-Level Synthesis (Proc. of International Symposium on Electronic Design, Test and Applications (DELTA), pp. 87-92)
177.	2009/12	Automatic Instrumentation of Profilers for FPGA-based Design Space Exploration (Proc. of International Conference on Field-Programmable Technology (FPT), pp. 292-295)
178.	2009/11	Modeling Power Consumption of Applications in Wireless Communication Devices Using OS Level Profiles (Proc. of International SoC Design Conference (ISOCC), pp. 253-256)
179.	2009/08	Practical Energy-Aware Scheduling for Real-Time Multiprocessor Systems (Proc. of International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), pp. 383-392)
180.	2009/08	Real-Time Operating Systems for MPSoC (9th International Forum on Embedded MPSoC and Multicore (MPSoC))
181.	2009/05	Heuristics for Static Voltage Scheduling Algorithms on Battery-Powered DVS Systems (Proc. of International Conference on Embedded Software and Systems (ICESS), pp. 265-272)
182.	2009/04	A Case Study on MPEG4 Decoder Design with SystemBuilder (Proc. of International Symposium on VLSI Design, Automation and Test (VLSI-DAT), pp. 355-358)
183.	2009/04	Allocation of Scratch-Pad Memory in Multi-Task Systems (Proc. of International Symposium on VLSI Design, Automation and Test (VLSI-DAT), pp. 68-71)
184.	2009/03	A Case Study on AES Encryption System Design with SystemBuilder (Proc. of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 283-288)
185.	2009/01	Analyzing and Optimizing Energy Efficiency of Algorithms on DVS Systems: A First Step towards Algorithmic Energy Minimization (Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 727-732)
186.	2009/01	Software Development and Programming of Multicore LSI (Full-Day Tutorial, Asia and South Pacific Design Automation Conference (ASP-DAC))
187.	2009/01	The CHStone Benchmark Suite for Practical C-based High-Level Synthesis (ECSI and USB Workshop on High Level Synthesis: Next Step to Efficient ESL Design in conjunction with Asia and South Pacific Design Automation Conference (ASP-DAC) and Electronic Design and Solution Fiair (EDSFair))
188.	2008/12	A Generalized Framework for System-Wide Energy Savings in Hard Real-Time Embedded Systems (Proc. of International Conference on Embedded and Ubiquitous Computing (EUC), pp. 206-213)
189.	2008/11	A Generalized Framework for Energy Savings in Real-Time Multiprocessor Systems (Proc. of International SoC Design Conference (ISOCC), Invited paper, LG Electronics best paper award, pp. 44-49)
190.	2008/11	Behavioral Partitioning with Exploiting Function-Level Parallelism (Proc. of International SoC Design Conference (ISOCC), pp. 121-124)
191.	2008/11	Real-Time Operating Systems for Multicore Embedded Systems (Proc. of International SoC Design Conference (ISOCC), Invited paper, pp. 62-67)
192.	2008/11	The Problems of SOC Industry (technology, market, careers, engineers, education) (Panel, International SoC Design Conference (ISOCC))
193.	2008/07	Energy Efficiency of Scratch-Pad Memory at 65 nm and Below: An Empirical Study (Proc. of International Conference on Embedded Software and Systems (ICESS), pp. 93-97)
194.	2008/06	The CHStone Benchmark Suite for Practical C-based High-Level Synthesis (Poster presentation, ECSI Workshop on High-Level Synthesis: Back to the Future in conjunction with Design Automation Conference (DAC))
195.	2008/05	CHStone: A Benchmark Program Suite for Practical C-Based High-Level Synthesis (Proc. of International Symposium on Circuits and Systems (ISCAS), pp. 1192-1195)
196.	2008/01	Improved Policies for Drowsy Caches in Embedded Processors (Proc. of International Symposium on Electronic Design, Test and Applications (DELTA), pp. 362-367)
197.	2007/12	A Software Framework for Energy and Performance Tradeoff in Fixed-Priority Hard Real-Time Embedded Systems (Proc. of International Conference on Embedded and Ubiquitous Computing (EUC), Springer Lecture Notes in Computer Science (LNCS) 4808, pp. 13-24)
198.	2007/10	Calling Software Functions from Hardware Functions in High-Level Synthesizer CCAP (Proc. of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 357-360)
199.	2007/10	Hardware/Software Covalidation with FPGA and RTOS Model (Proc. of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 488-494)
200.	2007/10	Speed Improvement of AES Encryption using Hardware Acclererators Synthesized by C Compatible Architecture Prototyper (CCAP) (Proc. of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 130-134)
201.	2007/08	Scheduling Algorithms for I/O Blockings with a Multi-frame Task Model (Proc. of International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), pp. 386-393)
202.	2007/06	RTOS-Centric Cosimulation of MPSoC (7th International Forum on Application-Specific Multi-Processor SoC (MPSoC))
203.	2007/05	A Hardware/Software Cosimulator with RTOS Supports for Multiprocessor Embedded Systems (Proc. of International Conference on Embedded Software and Systems (ICESS), Springer Lecture Notes in Computer Science (LNCS) 4523, pp. 283-294)
204.	2007/05	Behavioral Synthesis of Double-Precision Floating-Point Adders with Function-Level Transformations: A Case Study (Proc. of International Conference on Embedded Software and Systems (ICESS), Springer Lecture Notes in Computer Science (LNCS) 4523, pp. 261-270)
205.	2007/05	Power Optimization for Embedded System Idle Time in the Presence of Periodic Interrupt Services (Proc. of International Embedded Systems Symposium (IESS), Springer IFIP 231, pp. 241-254)
206.	2007/03	Complexity-Constrained Partitioning of Sequential Programs for Efficient Behavioral Synthesis (Proc. of Great Lakes Symposium on VLSI (GLSVLSI), pp. 365-370)
207.	2007/01	RTOS and Codesign Toolkit for Multiprocessor Systems-on-Chip (Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC), Invited paper, pp. 336-341)
208.	2006/10	An Extension Course for Training Trainers of Embedded Software (Proc. of 2nd Workshop on Embedded Systems Education (WESE), pp. 95-102)
209.	2006/08	Function Call Optimization in Behavioral Synthesis (EUROMICRO Conference on Digital System Design (DSD), pp. 522-529)
210.	2006/04	An Analysis of Learner's Activities in Embedded Software Programming Practices (Short paper, Proceedings of 19th Conference on Software Engineering Education and Training Workshops (CSEETW))
211.	2006/04	Communication Interfaces for System Level Design (Proc. of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 21-28)
212.	2006/04	High-Level Synthesis of Variable Accesses and Function Calls in Software Compatible Hardware Synthesizer CCAP (Proc. of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 29-34)
213.	2005/11	Cosimulation of ITRON-Based Embedded Software with SystemC (Proc. of International High Level Design Validation and Test Workshop (HLDVT), pp. 71-76)
214.	2005/09	A GA-Based Scheduling Method for FlexRay Systems (Proc. of International Conference on Embedded Software (EMSOFT), pp. 110-113)
215.	2005/09	NEXCESS: Nagoya University Extension Courses for Embedded Software Specialists (Proc. of 1st Workshop on Embedded Systems Education (WESE), pp. 16-20)
216.	2005/08	An Efficient Search Algorithm of Worst-Case Cache Flush Timings (Proc. of International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), pp. 45-52)
217.	2005/04	An RTOS-Based Approach to Design and Validation of Embedded Systems (Proc. of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), pp. 185-187)
218.	2004/09	RTOS-Centric Hardware/Software Cosimulator for Embedded System Design (Proc. of International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 158-163)
219.	2004/07	System-Level Design Tools and RTOS for Multiprocessor SoC (4th International Forum on Application-Specific Multi-Processor SoC (MPSoC))
220.	2003/10	Data Organization Exploration for Low-Energy Address Buses (Proc. of the First Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia), pp. 128-133)
221.	2003/04	A Front-end for Better Handling of High-level Hardware Descriptions (Proc. of 11th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 121-128)
222.	2002/11	A Framework for Bitwidth Optimization in System-on-Chip Design (1st Workshop on Application Specific Processors (WASP))
223.	2002/10	Data Memory Design Considering Effective Bitwidth for Low-Energy Embedded Systems (Proc. of 15th International Symposium on System Synthesis (ISSS), pp. 201-206)
224.	2002/03	Automatic Verification of In-Order Execution in Microprocessors with Fragmented Pipelines and Multicycle Functional Units (Proc. of Design Automation and Test in Europe (DATE), pp. 36-43)
225.	2002/01	Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language (Proc. of Joint Conference on VLSI Design (VLSI) and Asia and Sout Pacific Design Automation Conference (ASP-DAC), pp. 458-463)
226.	2001/10	Modeling Fixed-Priority Preemptive Multi-Task Systems in SpecC (Proc. of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 93-100)
227.	2001/01	New Directions in Compiler Technology for Embedded Systems (Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC), Embedded tutorial, pp. 409-414)
228.	2001/01	Satisfying Timing Constraints of Preemptive Real-Time Tasks through Task Layout Technique (Proc. 14th International Conference on VLSI Design, pp. 97-102)
229.	2000/11	Verification of In-Order Execution in Pipelined Processors (Proc. of 5th International High Level Design Validation and Test Workshop (HLDVT), pp. 40-44,)
230.	2000/05	Program Path Analysis to Bound Cache-Related Preemption Delay in Preemptive Real-Time Systems (Proc. of 8th International Workshop on Hardware/Software Codesign (CODES), pp. 67-71)
231.	2000/04	Task Layout Generation to Minimize Cache Miss Penalty for Preemptive Real Time Tasks: An ILP Approach (Proc. of 9th Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 202-208)
232.	1999/11	Modeling and Verification of Processor Pipelines in SOC Design Exploration (Proc. of 4rd International High Level Design Validation and Test Workshop (HLDVT), pp. 10-16)
233.	1999/10	Architecture Description Languages for Systems-on-Chip Design (Proc. of 6th Asia Pacific Conference on cHip Design Languages (APCHDL), Invited paper, pp. 109-116)
234.	1999/10	Automatic Software Toolkit Generation for Embedded Systems-on-Chip (Proc. of International Conference on VLSI and CAD (ICVC), Embedded tutorial, pp. 107-116)
235.	1999/09	A Retargetable Compilation for Embedded System Design Considering Variable Precisions (4th International Workshop on Software and Compilers for Embedded Systems (SCOPES))
236.	1998/12	Instruction Encoding Techniques for Area Minimization of Instruction ROM (Proc. of 11th International Symposium on System Synthesis (ISSS), pp. 125-130)
237.	1998/12	Statistical Performance-Driven Module Binding in High-Level Synthesis (Proc. of 11th International Symposium on System Synthesis (ISSS), pp. 66-71)
238.	1998/11	Criteria of Performance Verification and Test for Core-Based LSIs (Proc. of 3rd International High Level Design Validation and Test Workshop (HLDVT), pp. 116-119)
239.	1998/07	A Programming Language for Processor Based Embedded Systems (Proc. of Asia Pacific Conference on Hardware Description Languages (APCHDL), pp. 89-94)
240.	1998/07	A Soft-Core Processor Architecture for Embedded System Design (Proc. of Asia Pacific Conference on Hardware Description Languages (APCHDL), pp. 154-159)
241.	1998/07	Variable Size Analysis for Datapath Width Optimization (Proc. of Asia Pacific Conference on Hardware Description Languages (APCHDL), pp. 69-74)
242.	1998/04	A Framework for Application Specific System Design (Posters and research demonstrations, 20th International Conference on Software Engineering (ICSE))
243.	1998/03	An Embedded Software Programming Language for Application Specific Datapath Width Processors (Poster presentation, 6th International Workshop on Hardware/Sotware Codesign (Codes/CASHE))
244.	1998/02	Instruction Scheduling for Power Reduction in Processor-Based System Design (Proc. of Design Automation and Test in Europe (DATE), pp. 855-860)
245.	1998/02	Module Selection Using Manufacturing Information (Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 275-281)
246.	1997/08	Embedded System Design Using Soft-Core Processor and Valen-C (Proc. of 4th Asia Pacific Conference on Hardware Description Languages (APCHDL), Invited paper, pp. 121-130)
247.	1997/06	Memory-CPU Size Optimization for Embedded System Designs (Proc. of 34th Design Automation Conference (DAC), pp. 246-251)
248.	1996/11	Size-Constrained Code Placement for Cache Miss Rate Reduction (Proc. of 9th International Symposium on System Synthesis (ISSS), pp. 96-101)
249.	1996/11	The Satsuki Integrated Processor Synthesis and Compiler Generation System (Proc. of 6th Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 135-142)
250.	1996/03	Optimal Code Placement of Embedded Software for Instruction Caches (Proc. of European Design and Test Conference (ED&TC), pp. 96-101)
251.	1995/08	Hardware-Software Codesign with a Soft-Core Processor (Proc. of 5th Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 79-84)
252.	1994/10	Compiler Generator for Hardware/Software Codesign (Proc. of 2nd Asia Pacific Conference on Hardware Description Languages (APCHDL), pp. 267-270)
253.	1993/12	Compiler Generation from Hardware Description Language (Proc. of 1st Asian Pacific Conference on Hardware Description Languages, Standards & Applications (APCHDLSA), pp. 76-78)