研究者学術情報データベース

オチ　ヒロユキ
越智　裕之
OCHI HIROYUKI

所属情報理工学部情報理工学科

職名教授

論文
1.	2023/04/13	Nonvolatile Storage Cells Using FiCC for IoT Processors with Intermittent Operations │ IEICE Transactions on Electronics │ E106.C (10),546-555頁 (共著)
2.	2023/02/10	A CMOS-compatible Non-volatile Memory Element using Fishbone-in-cage Capacitor │ IPSJ Transactions on System and LSI Design Methodology │ 16,35-44頁 (共著)
3.	2022/06/23	Via-switch FPGA with transistor-free programmability enabling energy-efficient near-memory parallel computation │ Japanese Journal of Applied Physics │ 61 (SM0804),1-7頁 (共著)
4.	2019/07	Low-Power Crossbar Switch With Two-Varistor Selected Complementary Atom Switch (2V-1CAS; Via-Switch) for Nonvolatile FPGA │ IEEE Transactions on Electron Devices │ 66 (8),3331-3336 (共著)
5.	2018/12	Sensor signal processing using high-level synthesis with a layered architecture │ IEEE Embedded Systems Letters │ 10 (4),119-122 (共著)
6.	2018/12	Via-switch FPGA: Highly-dense Mixed-grained Reconfigurable Architecture with Overlay Via-switch Crossbars │ IEEE Transactions on Very Large Scale Integration (VLSI) Systems │ 26 (9),2723-2736 (共著)
7.	2017/07	Area-efficient LUT-like Programmable Logic Using Atom Switch and its Delay-optimal Mapping Algorithm │ IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences │ E100-A (7),1418-1426 (共著)
8.	2016/12	Range Limiter Using Connection Bounding Box for SA-based Placement of Mixed-grained Reconfigurable Architecture │ IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences │ E99-A (12),2328-2334 (共著)
9.	2015/07	An Error Correction Scheme Through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs │ IEICE Transactions on Electronics │ E98-C (7),741-750 (共著)
10.	2014/12	Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-based Design and Its Irradiation Testing │ IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences │ Vol.E97-A (12),2518-2529 (共著)
11.	2013/12	耐ソフトエラー再構成可能アーキテクチャ │ 日本信頼性学会誌「信頼性」 │ 35 (8),431-432 (共著)
12.	2013/04	A Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis │ IEICE Transactions on Electronics │ Vol.E96-C (4),(454,462) (共著)
13.	2013/04	Parallel Acceleration Scheme for Monte Carlo Based SSTA using Generalized STA Processing Element │ IEICE Transactions on Electronics │ E96-C (4),(473-481) (共著)
14.	2012/12	A High-Throughput Pipelined Parallel Architecture for JPEG XR Encoding │ ACM Transactions in Embedded Computing Systems (TECS) │ Vol.11 (3),Article No. 72 (共著)
15.	2012/12	A Variability-Aware Energy-Minimization Strategy for Subthreshold Circuits │ IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences │ Vol.E95-A (12),(2242-2250) (共著)
16.	2012/12	Bayesian Estimation of Multi-Trap RTN Parameters using Markov Chain Monte Carlo Method │ IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences │ Vol.E95-A (12),(2272-2283) (共著)
17.	2011/05	Hardware Accelerator for Robust Object Tracking Using a Cascade Particle Filter │ Journal of Signal Processing │ Vol.15 (5),(215-223) (共著)
18.	2010/12	Reliability Evaluation Environment for Exploring Design Space of Coarse-Grained Reconfigurable Architectures │ IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences │ Vol.E93-A (12),(2524-2532) (共著)
19.	2009/11	Hardware Accelerator for Run-Time Learning Adopted in Object Recognition with Cascade Particle Filter │ IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences │ Vol.E92-A (11),(2801-2808) (共著)
20.	2009/10	メディアストリーミングにおける高速移動通信網に適した動的符号化レート制御手法 │ 情報処理学会論文誌 │ Vol.50 (10),(2532-2542) (共著)
21.	2009/08	Efficient Memory Organization Framework for JPEG2000 Entropy Codec │ IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences │ Vol.E92-A (8),(1970-1977) (共著)
22.	2009/02	An Asynchronous IEEE-754-Standard Single-Precision Floating-Point Divider for FPGA │ IPSJ Trans. on System LSI Design Methodology │ Vol.2,(103-113) (共著)
23.	2008/12	Autonomous Repair Fault Tolerant Dynamic Reconfigurable Device │ IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences │ Vol.E91-A (12),(3612-3621) (共著)
24.	2007/04	A Simulation Platform for Designing Cell-Array-Based Self-Reconfigurable Architecture │ IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences │ Vol.E90-A (4),(784-791) (共著)
25.	2007/04	Network Processor for High-Speed Network and Quick Programming │ Journal of Circuits, Systems, and Computers │ Vol.16 (1),(65-79) (共著)
26.	2006/12	Fault Tolerant Dynamic-Reconfigurable Device based on EDAC with Rollback │ IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences │ Vo.E89-A (12),(3652-3658) (共著)
27.	2005/06	微細テクノロジ向けDRCルールファイルからの設計規則抽出とその可視化 │ 情報処理学会論文誌 │ Vol.46 (6),(1404-1415) (共著)
28.	2005/04	An Integrated Approach of Variable Ordering and Logic Mapping into LUT-Array-Based PLD │ IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences │ Vol.E88-A (4),(907-914) (共著)
29.	2003/12	Development of an IP Library of IEEE-754-Standard Single-Precision Floating-Point Dividers │ IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences │ Vol.E86-A (12),(3020-3027) (共著)
30.	2003/05	DRCルールファイルからの設計規則抽出とその可視化 │ 情報処理学会論文誌 │ Vol.44 (5),(1255-1265) (共著)
31.	2000/12	An Algorithm for Generating Generic BDDs │ IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences │ Vol.E83-A (12),(2505-2512) (共著)
32.	1999/04	Datapath-Layout-Driven Design for Low-Power FPGA Implementation │ 情報処理学会論文誌 │ Vol.40 (4),(1529-1537) (共著)
33.	1999/04	FPAccA: フィールドプログラマブルアキュムレータアレイ ―FPAccA model 1.0チップの設計と評価 │ 情報処理学会論文誌 │ Vol.40 (4),(1717-1725) (単著)
34.	1997/10	ASAver.1: An FPGA-Based Education Board for Computer Architecture/System Design │ IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences │ Vol.E80-A (10),(1826-1833) (共著)
35.	1996/12	A Zero-Suppressed BDD Package with Pruning and Its Application to GRM Minimization │ IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences │ Vol.E79-A (12),(2134-2139) (単著)
36.	1996/10	Formal Design Verification of Combinational Circuits Specified by Recurrence Equations │ IEICE Trans. Inf. and Syst. │ Vol.E79-D (10),(1431-1435) (共著)
37.	1991/11	A Vector Algorithm for Manipulating Boolean Functions Based on Shared Binary Decision Diagrams │ Supercomputer │ vol.VIII (6),(101-118) (共著)
38.	1989/09	共有展開に基づくベクトル計算機向き論理関数素項生成法 │ 信学論D-I分冊 │ Vol.J72-D-I (9),(652-659) (共著)