研究者学術情報データベース

オチ　ヒロユキ
越智　裕之
OCHI HIROYUKI

所属情報理工学部情報理工学科

職名教授

学会発表
1.	2023/11/07	２線分による片補正を用いた対数型近似乗算器 (第203回システムとLSIの設計技術研究発表会 (SLDM WIP Forum 2023）)
2.	2023/10/26	Finding All Solutions of Multi-terminal Numberlink Problem Utilizing Top-down ZDD Construction (2023 IEEE 15th International Conference on ASIC (ASICON))
3.	2023/09/08	Approximate Logarithmic Multipliers Using Half Compensation with Two Line Segments (2023 IEEE 36th International System-on-Chip Conference (SOCC))
4.	2023/08/31	トップダウンZDD構築法を用いたDSPブロック向けテクノロジマッピング最適解全列挙アルゴリズム (DAシンポジウム)
5.	2022/10/25	Feasibility Study of DSP Block Mapping Algorithms for FPGAs Utilizing SAT-solver and Top-down ZDD Construction (The 24th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2022))
6.	2022/08/09	Nonvolatile Flip-Flops Using FiCC for IoT Processors with Intermittent Operations (65th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2022))
7.	2022/04/22	Zero-standby-power Nonvolatile Standard Cell Memory Using FiCC for IoT Processors with Intermittent Operations (IEEE Symposium on Low-Power and High-Speed Chips (COOL CHIPS 25))
8.	2021/12/25	ZDDを用いたDSP向けテクノロジマッピングの実現可能性検討 (第47回パルテノン研究会)
9.	2021/12/25	信号処理の高効率実装に向けた原子スイッチFPGA向けDSPの設計 (第47回パルテノン研究会)
10.	2021/09/01	間欠動作を行うIoT向けプロセッサに適したFiCCを用いた不揮発スタンダードセルメモリの実測評価 (DAシンポジウム)
11.	2021/04/16	Nonvolatile SRAM Using Fishbone-in-Cage Capacitor in a 180 nm Standard CMOS Process for Zero-standby and Instant-powerup Embedded Memory on IoT (IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 24))
12.	2021/03/29	A Feasibility Study on Realizing General-purpose Technology Mapper for DSPs of FPGAs Using Exhaustive Search (The 23rd Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2021))
13.	2021/03/10	FiCCを用いた不揮発スタンダードセルメモリ (電子情報通信学会総合大会2021)
14.	2021/03/03	太陽電池混載チップでのCMOS互換回路による電源電圧変動に頑強な温度センサの測定 (信学技報, vol. 120, no. 400, VLD2020-74, pp. 32-37)
15.	2021/02/03	MUX Granularity-Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA (The 24th Design, Automation and Test in Europe Conference (DATE 2021))
16.	2020/09/08	FPGAのDSPブロック向け汎用的テクノロジマッパの網羅的探索による実現可能性検討 (DAシンポジウム2020)
17.	2020/03/04	Via-Switch FPGAを対象とする算術演算アプリケーション回路の実装方式検討 (信学技報)
18.	2020/02/19	Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications (2020 International Solid-State Circuits Conference (ISSCC 2020))
19.	2019/10/22	Wire Load Model for Rapid Power Consumption Evaluation in Early Design Stage of Via-Switch FPGA (Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI))
20.	2019/10/21	Improving Global Motion Compensation for Frame Interpolation with High-Resolution and High-Frame-Rate Video (Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI))
21.	2019/08/28	FiCCを用いたCMOS互換な不揮発性メモリ素子の閾値電圧特性の測定ならびに読み出し方式検討 (DAシンポジウム)
22.	2019/03/07	2種類の情報をもつ動画像を用いたフレーム補間におけるグローバルモーション補償の精度向上に向けた検討 (信学技報, vol. 118, no. 473, SIS2018-47, pp. 53-58)
23.	2019/03/06	Raspberry Pi向けの低消費エネルギーな動画像符号化方式の検討 (信学技報, vol. 118, no. 473, SIS2018-38, pp. 5-9)
24.	2019/02/28	高速かつ高ノイズマージンな65nm FD-SOI向けドミノ高基数ツリー加算器設計 (信学技報, vol. 118, no. 457, VLD2018-112, pp. 115-120)
25.	2019/02/27	ビアスイッチFPGAの消費電力評価のための配線容量モデル (信学技報, vol. 118, no. 457, VLD2018-97, pp. 25-30)
26.	2018/12/07	FiCCを用いたCMOS互換な超低消費電力不揮発性メモリ素子の特性測定回路の設計と試作 (信学技報, vol. 118, no. 334, VLD2018-65, pp. 183-188)
27.	2018/03/27	Novel Implementation of FFT for Mixed Grained Reconfigurable Architecture Using Via-switch (Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI))
28.	2018/03/27	Routing Method Considering Programming Constraint of Reconfigurable Device Using Via-switch Crossbars (Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI))
29.	2018/02/28	2種類の情報をもつ動画像を用いたフレーム補間の前景除去と輪郭抽出による品質向上 (信学技報, vol. 117, no. 455, VLD2017-98, pp. 55-60)
30.	2018/01/19	ビアスイッチ向けプログラマブルロジック0-1-A-~A LUTの電力効率について (信学技報, vol. 117, no. 377, VLD2017-80, pp. 107-112)
31.	2017/11/07	ビアスイッチを用いた粒度混合再構成可能アーキテクチャへの最適なFFT回路実装 (信学技報, vol. 117, no. 273, VLD2017-38, pp. 67-72)
32.	2017/11/07	ビアスイッチクロスバを用いた再構成可能デバイスのプログラム制約を考慮する配線手法 (信学技報, vol. 117, no. 273, VLD2017-39, pp. 73-78)
33.	2017/09/06	Placement Algorithm for Mixed-Grained Reconfigurable Architecture with Dedicated Carry Chain (IEEE International System-on-Chip Conference (SOCC))
34.	2017/09/06	Selectable Grained Reconfigurable Architecture (SGRA) and Its Design Automation (IEEE International System-on-Chip Conference (SOCC))
35.	2017/06/20	システムと信号処理サブソサイエティの役割～チュートリアル講演の位置づけ～ (信学技報, vol. 117, no. 96, CAS2017-19, pp. 99-99)
36.	2017/06/20	太陽電池混載チップ向けCMOS互換温度・照度センサ (信学技報, vol. 117, no. 97, VLD2017-25, pp. 113-118)
37.	2017/06/19	専用キャリーチェーンを考慮した粒度混合再構成可能アーキテクチャ向け配置アルゴリズム (信学技報, vol. 117, no. 97, VLD2017-7, pp. 19-24)
38.	2017/06/19	粒度選択型再構成可能アーキテクチャSGRAとその設計自動化 (信学技報, vol. 117, no. 97, VLD2017-8, pp. 25-30)
39.	2017/03/02	FiCC:高集積向け耐クロストークノイズメタルフリンジキャパシタ (信学技報, vol. 116, no. 478, pp. 43-47)
40.	2017/03/02	ウエハスケールマスクROMの階層的データ読み出し回路の高信頼化 (信学技報, vol. 116, no. 478, pp. 49-54)
41.	2017/02/06	低電力FPGAを実現するビアスイッチ技術を用いた大規模クロスバースイッチの実証 (信学技報, vol. 116, no. 450, SDM2016-144, pp. 29-34)
42.	2016/12/06	50×20 crossbar switch block (CSB) with two-varistors (a-Si/SiN/a-Si) selected complementary atom switch for a highly-dense reconfigurable logic (62nd International Electron Devices Meeting (IEDM 2016))
43.	2016/11/29	原子移動型スイッチを用いた小面積なプログラマブルロジックとそのための遅延最適なテクノロジマッピング手法 (信学技報, vol.116, no.332, pp.29-34)
44.	2016/11/28	マイクロエナジーハーベスティングのための2段昇圧型チャージポンプ回路 (信学技報, vol.116, no.330, pp.13-18)
45.	2016/10/25	A Method for Recognizing a Breaking Sound of a Window Glass for Realizing a Low-power Security Surveillance System Using FPGA (The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2016))
46.	2016/10/25	Range Limiter using Connection Bounding Box for SA-based Placement of Mixed-Grained Reconfigurable Architecture (The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2016))
47.	2016/09/28	原子スイッチを用いた再構成可能デバイスによるCNNの実装の実現可能性検討 (2016年度情報処理学会関西支部支部大会)
48.	2016/09/14	Novel processor architecture for onboard infrared sensors (Proceedings of SPIE Infrared Remote Sensing and Instrumentation XXIV, vol. 9973)
49.	2016/08/31	A Highly-dense Mixed Grained Reconfigurable Architecture with Overlay Crossbar Interconnect using Via-switch (26th International Conference on Field-Programmable Logic and Applications (FPL 2016))
50.	2016/06/07	Highly-dense Mixed Grained Reconfigurable Architecture with Via-switch (53rd Design Automation Conference (DAC 2016))
51.	2015/12/07	A Novel Two-Varistors (a-Si/SiN/a-Si) Selected Complementary Atom Switch (2V-1CAS) for Nonvolatile Crossbar Switch with Multiple Fan-outs (61st International Electron Devices Meeting (IEDM 2015))
52.	2015/10/08	A -0.5V-input Voltage Booster Circuit for On-chip Solar Cells in 0.18µm CMOS Technology (15th International Symposium on Communications and Information Technologies (ISCIT 2015))
53.	2015/10/08	Area-efficient LUT-like Programmable Logic Using Atom Switch and Its Mapping Algorithm (15th International Symposium on Communications and Information Technologies (ISCIT 2015))
54.	2015/09/28	FPGAを用いた低消費電力な防犯システムの実装に向けた窓ガラスの割れる音の認識手法 (2015年度情報処理学会関西支部支部大会)
55.	2015/04/17	センサの知能化に適したプロセッサアーキテクチャの考察 (信学技報, vol. 115, no. 8, DC2015-8, pp. 43-48)
56.	2015/03/16	On the Impact of Initial Placement to SA-Based Placement for Mixed-Grained Reconfigurable Architecture (19th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI))
57.	2015/01/20	Reliability-Configurable Mixed-Grained Reconfigurable Array Compatible with High-Level Synthesis (ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC))
58.	2014/03	Experimental validation of minimum operating-voltage-estimation for low supply voltage circuits (International Symposium on Quality Electrical Design (ISQED))
59.	2013/12/11	Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design (International Conference on Reconfigurable Computing and FPGAs (ReConFig))
60.	2013/11/13	Reliability-configurable mixed-grained reconfigurable array supporting C-to-array mapping and its radiation testing (IEEE Asian Solid-State Circuits Conference (A-SSCC))
61.	2013/10/21	A coarse-grained reconfigurable architecture to enhance soft and hard-error tolerance using time redundancy (18th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI))
62.	2013/09/05	Sealed mask ROM wafer with 5 mm magnetic resonant coupling for long-term digital data preservation (26th IEEE Intl. System-on-Chip Conference (SOCC))
63.	2013/07/05	低電源電圧におけるフリップフロップの故障モードの解析 (電子情報通信学会集積回路研究会)
64.	2013/07/01	Architecture for sealed wafer-scale mask ROM for long-term digital data preservation (28th Intl. Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC))
65.	2013/07/01	Histogram propagation based statistical timing analysis using dependent node selection (28th Intl. Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC))
66.	2013/05/20	動作合成に対応した信頼性可変混合粒度再構成可能アーキテクチャの検討 (信学技報, vol. 113, no. 52, RECONF2013-8, pp. 41-46)
67.	2013/05/02	Fast and memory-efficient GPU implementations of Krylov subspace methods for efficient power grid analysis (Great Lakes Symposium on VLSI (GLSVLSI))
68.	2013/03/20	A cost-effective selective TMR for heterogeneous coarse-grained reconfigurable architectures based on DFG-level vulnerability analysis (Design, Automation & Test in Europe (DATE))
69.	2013/03/20	Hot-swapping architecture with back-biased testing for mitigation of permanent faults in functional unit array (Design, Automation & Test in Europe (DATE))
70.	2013/03/06	High-speed DFG-level SEU vulnerability analysis for applying selective TMR to resource-constrained CGRA (International Symposium on Quality Electrical Design (ISQED))
71.	2013/03/06	Multi-trap RTN parameter extraction based on bayesian inference (International Symposium on Quality Electrical Design (ISQED))
72.	2013/01/23	Realization of frequency-domain circuit analysis through random walk (ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC))
73.	2012/03	GPU Acceleration of Cycle-Based Soft-Error Simulation for Reconfigurable Array Architectures (Proc. 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI))
74.	2012/03	Hardware Architecture for Accelerating Monte Carlo Based SSTA using Generalized STA Processing Element (Proc. 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI))
75.	2012/03	Statistical Observations of NBTI-Induced Threshold Voltage Shifts on Small Channel-Area Devices (Proc. Intl. Symposium on Quality Electrical Design (ISQED))
76.	2012/01	Acceleration Scheme for Monte Carlo Based SSTA using Generalized STA Processing Element (Proc. ACM/IEEE Intl. Workshop on Timing Issues (TAU))
77.	2011/09	A Design Strategy for Sub-Threshold Circuits Considering Energy-Minimization and Yield-　Maximization (Proc. IEEE Intl. SOC Conference (SOCC))
78.	2011/09	A Device Array for Efficient Bias-Temperature Instability Measurements (Proc. European Solid-State Device Research Conference (ESSDERC))
79.	2011/06	A Stress- Parallelized Device Array for Efficient Bias-Temperature Stability Measurement (Proc. IEEE Intl. Workshop on Design for Manufacturability and Yield (DFM&Y))
80.	2011/05	Acceleration of Random-Walk-Based Linear Circuit Analysis using Importance Sampling (Proc. GLSVLSI 2011)
81.	2010/11	Sequential Importance Sampling for Low-Probability and High-Dimensional SRAM Yield Analysis (Proc. IEEE/ACM 2010 Intl. Conference on Computer-Aided Design (ICCAD 2010))
82.	2010/10	A Tile Based Reconfigurable Architecture with Dual ALU-Array/processor Operating Mode Capability (Proc. 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI))
83.	2010/09	A Routing Architecture Exploration for Coarse- Grained Reconfigurable Architecture with Automated SEU-tolerance Evaluation (Proc. 23rd IEEE Intl. SOC Conference (SOCC 2010))
84.	2010/05	Small Delay and Area Overhead Process Parameter Estimation Through Path-Delay Inequalities (Proc. IEEE Intl. Symposium on Circuits and Systems (ISCAS))
85.	2010/04	Path Clustering for Adaptive Test (Proc. IEEE VLSI Test Symposium (VTS))
86.	2009/09/01	Hot-Swapping Architecture Extension for Mitigation of Permanent Functional Unit Faults (Proc. 19th Intl. Conference on Field Programmable Logic and Applications (FPL))
87.	2009/08	Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability (Proc. Intl. Conference on Field Programmable Logic and Applications (FPL))
88.	2009/06	Digital Rosetta Stone: a Sealed Permanent Memory with Inductive-Coupling Power and Data Link (Proc. Symposium on VLSI Circuits)