Researcher Database

OCHI HIROYUKI

Department / Course College of Information Science and Engineering Department of Information Science and Engineering

Title / Position Professor

Academic conference presentation
1.	2023/10/26	Finding All Solutions of Multi-terminal Numberlink Problem Utilizing Top-down ZDD Construction (2023 IEEE 15th International Conference on ASIC (ASICON))
2.	2023/09/08	Approximate Logarithmic Multipliers Using Half Compensation with Two Line Segments (2023 IEEE 36th International System-on-Chip Conference (SOCC))
3.	2023/08/31	Algorithm for Enumerating All Optimal Solutions of DSP Block Mapping Utilizing Top-down ZDD Construction (Design Automation Symposium)
4.	2022/10/25	Feasibility Study of DSP Block Mapping Algorithms for FPGAs Utilizing SAT-solver and Top-down ZDD Construction (The 24th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2022))
5.	2022/08/09	Nonvolatile Flip-Flops Using FiCC for IoT Processors with Intermittent Operations (65th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2022))
6.	2022/04/22	Zero-standby-power Nonvolatile Standard Cell Memory Using FiCC for IoT Processors with Intermittent Operations (IEEE Symposium on Low-Power and High-Speed Chips (COOL CHIPS 25))
7.	2021/09/01	Nonvolatile Standard Cell Memory Using FiCC for IoT Processors with Intermittent Operations (Design Automation Symposium)
8.	2021/04/16	Nonvolatile SRAM Using Fishbone-in-Cage Capacitor in a 180 nm Standard CMOS Process for Zero-standby and Instant-powerup Embedded Memory on IoT (IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 24))
9.	2021/03/29	A Feasibility Study on Realizing General-purpose Technology Mapper for DSPs of FPGAs Using Exhaustive Search (The 23rd Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2021))
10.	2021/03/10	Nonvolatile Standard-cell Memory using FiCC (IEICE General Conference 2021)
11.	2021/03/03	Measurement of Voltage-variation-tolerant Temperature Sensor for Standard CMOS Chip with On-chip Solar Cell (IEICE Tech. Rep., vol. 120, no. 400, VLD2020-74, pp. 32-37)
12.	2021/02/03	MUX Granularity-Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA (The 24th Design, Automation and Test in Europe Conference (DATE 2021))
13.	2020/09/08	A Feasibility Study on Realizing General-purpose Technology Mapper for DSPs of FPGAs Using Exhaustive Search (DA Symposium 2020)
14.	2020/03/04	A Study of Arithmetic-Oriented Application Implementations for Via-Switch FPGA
15.	2020/02/19	Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications (2020 International Solid-State Circuits Conference (ISSCC 2020))
16.	2019/10/22	Wire Load Model for Rapid Power Consumption Evaluation in Early Design Stage of Via-Switch FPGA (Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI))
17.	2019/10/21	Improving Global Motion Compensation for Frame Interpolation with High-Resolution and High-Frame-Rate Video (Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI))
18.	2019/08/28	Thereshold-voltage Measurement of CMOS-compatible Non-volatile Memory Element using FiCC and Consideration on its Read-out Method (Design Automation Symposium)
19.	2019/03/07	A Study of Global Motion Compensation for Frame Interpolation with High-Resolution and High-Frame Rate Video (IEICE Tech. Rep., vol. 118, no. 473, SIS2018-47, pp. 53-58)
20.	2019/03/06	A Study of Low-Energy Video Encoding Method for Raspberry Pi (IEICE Tech. Rep., vol. 118, no. 473, SIS2018-38, pp. 5-9)
21.	2019/02/28	High-Speed and Noise Tolerant High-Radix Tree Domino Adder in 65 nm FD-SOI Technology (IEICE Tech. Rep., vol. 118, no. 457, VLD2018-112, pp. 115-120)
22.	2019/02/27	Wire Load Model for Power Consumption Evaluation of Via-Switch FPGA (IEICE Tech. Rep., vol. 118, no. 457, VLD2018-97, pp. 25-30)
23.	2018/12/07	Design and fabrication of characteristics measurement circuit for CMOS-compatible ultra-low-power non-volatile memory element using FiCC (IEICE Tech. Rep., vol. 118, no. 334, VLD2018-65, pp. 183-188)
24.	2018/03/27	Novel Implementation of FFT for Mixed Grained Reconfigurable Architecture Using Via-switch (Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI))
25.	2018/03/27	Routing Method Considering Programming Constraint of Reconfigurable Device Using Via-switch Crossbars (Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI))
26.	2018/02/28	A Study on Quality Improvement of Frame Interpolation Method with High-Resolution and High-Frame Rate Video Using Foreground Elimination and Contour Extraction (Technical Report of IEICE, vol. 117, no. 455, VLD2017-98, pp. 55-60)
27.	2018/01/19	A study on the power efficiency of via-switch oriented programmable logic 0-1-A-~A LUT (Technical Report of IEICE, vol. 117, no. 377, VLD2017-80, pp. 107-112)
28.	2017/11/07	Novel Implementation of FFT for Mixed Grained Reconfigurable Architecture Using Via-switch (Technical Report of IEICE, vol. 117, no. 273, VLD2017-38, pp. 67-72)
29.	2017/11/07	Routing method considering programming constraint of reconfigurable device using via-switch crossbars (Technical Report of IEICE, vol. 117, no. 273, VLD2017-39, pp. 73-78)
30.	2017/09/06	Placement Algorithm for Mixed-Grained Reconfigurable Architecture with Dedicated Carry Chain (IEEE International System-on-Chip Conference (SOCC))
31.	2017/09/06	Selectable Grained Reconfigurable Architecture (SGRA) and Its Design Automation (IEEE International System-on-Chip Conference (SOCC))
32.	2017/06/20	The role of System and Signal Processing Subsociety ---A milestone of tutorial lecture--- (IEICE Technical Report, vol. 117, no. 96, CAS2017-19, pp. 99-99)
33.	2017/06/20	CMOS-compatible Temperature and Illuminance Sensor for Solar-cell-embedded Chip (Technical Report of IEICE, vol. 117, no. 97, VLD2017-25, pp. 113-118)
34.	2017/06/19	Placement Algorithm for Mixed-Grained Reconfigurable Architecture with Dedicated Carry Chain (Technical Report of IEICE, vol. 117, no. 97, VLD2017-7, pp. 19-24)
35.	2017/06/19	Selectable Grained Reconfigurable Architecture (SGRA) and Its Design Automation (Technocal Report of IEICE, vol. 117, no. 97, VLD2017-8, pp. 25-30)
36.	2017/03/02	FiCC: Crosstalk Noise Hardened Metal Fringe Capacitor for High Integration (Technical Report of IEICE, vol. 116, no. 478, pp. 43-47)
37.	2017/03/02	Reliability enhancement of hierarchical data reading circuit of wafer scale mask ROM (Technical Report of IEICE, vol. 116, no. 478, pp. 49-54)
38.	2017/02/06	Large Scale Crossbar Switch Block (CSB) with Via-Switch for a Low-Power FPGA (IEICE Technical Report, vol. 116, no. 450, SDM2016-144, pp. 29-34)
39.	2016/12/06	50×20 crossbar switch block (CSB) with two-varistors (a-Si/SiN/a-Si) selected complementary atom switch for a highly-dense reconfigurable logic (62nd International Electron Devices Meeting (IEDM 2016))
40.	2016/11/29	Area-efficient LUT-like Programmable Logic Using Atom Switch and its Delay-optimal Mapping Algorithm (Technical Report of IEICE, vol.116, no.332, pp-29-34)
41.	2016/11/28	2-step Charge Pump Voltage Booster Circuit for Micro Energy Harvesting (Technical Report of IEICE, vol.116, no.330, pp.13-18)
42.	2016/10/25	A Method for Recognizing a Breaking Sound of a Window Glass for Realizing a Low-power Security Surveillance System Using FPGA (The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2016))
43.	2016/10/25	Range Limiter using Connection Bounding Box for SA-based Placement of Mixed-Grained Reconfigurable Architecture (The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2016))
44.	2016/09/28	A Feasibility Study on the Implementation of CNN using Atom-switch-based Reconfigurable Device (IPSJ Kansai-Branch Convention 2016)
45.	2016/09/14	Novel processor architecture for onboard infrared sensors (Proceedings of SPIE Infrared Remote Sensing and Instrumentation XXIV, vol. 9973)
46.	2016/08/31	A Highly-dense Mixed Grained Reconfigurable Architecture with Overlay Crossbar Interconnect using Via-switch (26th International Conference on Field-Programmable Logic and Applications (FPL 2016))
47.	2016/06/07	Highly-dense Mixed Grained Reconfigurable Architecture with Via-switch (53rd Design Automation Conference (DAC 2016))
48.	2015/12/07	A Novel Two-Varistors (a-Si/SiN/a-Si) Selected Complementary Atom Switch (2V-1CAS) for Nonvolatile Crossbar Switch with Multiple Fan-outs (61st International Electron Devices Meeting (IEDM 2015))
49.	2015/10/08	A -0.5V-input Voltage Booster Circuit for On-chip Solar Cells in 0.18µm CMOS Technology (15th International Symposium on Communications and Information Technologies (ISCIT 2015))
50.	2015/10/08	Area-efficient LUT-like Programmable Logic Using Atom Switch and Its Mapping Algorithm (15th International Symposium on Communications and Information Technologies (ISCIT 2015))
51.	2015/09/28	A Method for Recognizing a Breaking Sound of a Window Glass for Implementing a Low-power Security System Using FPGA (IPSJ Kansai-Branch Convention 2015)
52.	2015/04/17	A study of processor architecture suited for intelligent sensing system (IEICE Technical Report, vol. 115, no. 8, DC2015-8, pp. 43-48)
53.	2015/03/16	On the Impact of Initial Placement to SA-Based Placement for Mixed-Grained Reconfigurable Architecture (19th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI))
54.	2015/01/20	Reliability-Configurable Mixed-Grained Reconfigurable Array Compatible with High-Level Synthesis (ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC))
55.	2014/03	Experimental validation of minimum operating-voltage-estimation for low supply voltage circuits (International Symposium on Quality Electrical Design (ISQED))
56.	2013/12/11	Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design (International Conference on Reconfigurable Computing and FPGAs (ReConFig))
57.	2013/11/13	Reliability-configurable mixed-grained reconfigurable array supporting C-to-array mapping and its radiation testing (IEEE Asian Solid-State Circuits Conference (A-SSCC))
58.	2013/10/21	A coarse-grained reconfigurable architecture to enhance soft and hard-error tolerance using time redundancy (18th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI))
59.	2013/09/05	Sealed mask ROM wafer with 5 mm magnetic resonant coupling for long-term digital data preservation (26th IEEE Intl. System-on-Chip Conference (SOCC))
60.	2013/07/05	Failure mode analysis for flip-flops at low voltages (IEICE ICD)
61.	2013/07/01	Architecture for sealed wafer-scale mask ROM for long-term digital data preservation (28th Intl. Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC))
62.	2013/07/01	Histogram propagation based statistical timing analysis using dependent node selection (28th Intl. Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC))
63.	2013/05/20	Flexible reliability mixed-grained reconfigurable architecture supporting behavioral synthesis (IEICE Technical Report, vol. 113, no. 52, RECONF2013-8, pp. 41-46)
64.	2013/05/02	Fast and memory-efficient GPU implementations of Krylov subspace methods for efficient power grid analysis (Great Lakes Symposium on VLSI (GLSVLSI))
65.	2013/03/20	A cost-effective selective TMR for heterogeneous coarse-grained reconfigurable architectures based on DFG-level vulnerability analysis (Design, Automation & Test in Europe (DATE))
66.	2013/03/20	Hot-swapping architecture with back-biased testing for mitigation of permanent faults in functional unit array (Design, Automation & Test in Europe (DATE))
67.	2013/03/06	High-speed DFG-level SEU vulnerability analysis for applying selective TMR to resource-constrained CGRA (International Symposium on Quality Electrical Design (ISQED))
68.	2013/03/06	Multi-trap RTN parameter extraction based on bayesian inference (International Symposium on Quality Electrical Design (ISQED))
69.	2013/01/23	Realization of frequency-domain circuit analysis through random walk (ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC))
70.	2012/03	GPU Acceleration of Cycle-Based Soft-Error Simulation for Reconfigurable Array Architectures (Proc. 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI))
71.	2012/03	Hardware Architecture for Accelerating Monte Carlo Based SSTA using Generalized STA Processing Element (Proc. 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI))
72.	2012/03	Statistical Observations of NBTI-Induced Threshold Voltage Shifts on Small Channel-Area Devices (Proc. Intl. Symposium on Quality Electrical Design (ISQED))
73.	2012/01	Acceleration Scheme for Monte Carlo Based SSTA using Generalized STA Processing Element (Proc. ACM/IEEE Intl. Workshop on Timing Issues (TAU))
74.	2011/09	A Design Strategy for Sub-Threshold Circuits Considering Energy-Minimization and Yield-　Maximization (Proc. IEEE Intl. SOC Conference (SOCC))
75.	2011/09	A Device Array for Efficient Bias-Temperature Instability Measurements (Proc. European Solid-State Device Research Conference (ESSDERC))
76.	2011/06	A Stress- Parallelized Device Array for Efficient Bias-Temperature Stability Measurement (Proc. IEEE Intl. Workshop on Design for Manufacturability and Yield (DFM&Y))
77.	2011/05	Acceleration of Random-Walk-Based Linear Circuit Analysis using Importance Sampling (Proc. GLSVLSI 2011)
78.	2010/11	Sequential Importance Sampling for Low-Probability and High-Dimensional SRAM Yield Analysis (Proc. IEEE/ACM 2010 Intl. Conference on Computer-Aided Design (ICCAD 2010))
79.	2010/10	A Tile Based Reconfigurable Architecture with Dual ALU-Array/processor Operating Mode Capability (Proc. 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI))
80.	2010/09	A Routing Architecture Exploration for Coarse- Grained Reconfigurable Architecture with Automated SEU-tolerance Evaluation (Proc. 23rd IEEE Intl. SOC Conference (SOCC 2010))
81.	2010/05	Small Delay and Area Overhead Process Parameter Estimation Through Path-Delay Inequalities (Proc. IEEE Intl. Symposium on Circuits and Systems (ISCAS))
82.	2010/04	Path Clustering for Adaptive Test (Proc. IEEE VLSI Test Symposium (VTS))
83.	2009/09/01	Hot-Swapping Architecture Extension for Mitigation of Permanent Functional Unit Faults (Proc. 19th Intl. Conference on Field Programmable Logic and Applications (FPL))
84.	2009/08	Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability (Proc. Intl. Conference on Field Programmable Logic and Applications (FPL))
85.	2009/06	Digital Rosetta Stone: a Sealed Permanent Memory with Inductive-Coupling Power and Data Link (Proc. Symposium on VLSI Circuits)