研究者学術情報データベース

オオクラ　シュンスケ
大倉　俊介
OKURA SHUNSUKE

所属理工学部電子情報工学科

職名准教授

論文
1.	2023/05/21	A Study on a Feature Extractable CMOS Image Sensor for Low-Power Image Classification System │ Proceedings of 2023 International Image Sensor Workshop │ (P33) (共著)
2.	2023/05/21	A Study on Two Step Reset LOFIC Pixel to Reduce SNR Gap │ Proceedings of 2023 International Image Sensor Workshop │ (P10) (共著)
3.	2023/05/14	Backdoor Attack on Deep Neural Networks Triggered by Fault Injection Attack on Image Sensor Interface │ Sensors, MDPI AG │ 23 (10:4742) (共著)
4.	2023/05/04	An Area-Efficient up/down Double-Sampling Circuit for a LOFIC CMOS Image Sensor │ Sensors, MDPI AG │ 23 (9:4478) (共著)
5.	2023/02/28	Image classification with SVM for CMOS sensor generating a vector image │ Proceedings of the 2023 International Workshop on Nonlinear Circuits, Communication and Signal Processing │ ,1AM1-2-2 (共著)
6.	2023/01/25	Fundamental Study of Adversarial Examples Created by Fault Injection Attack on Image Sensor Interface │ 2022 Asian Hardware Oriented Security and Trust Symposium (AsianHOST) │ (共著)
7.	2022/12/12	A Variable-Resolution SAR ADC with 10-bit Image Capturing Mode and 5-bit Feature Extraction Mode │ Proceedings of 2022 International Workshop on Image Sensors and Systems │ (Poster-12) (共著)
8.	2022/12/12	An area efficient readout circuit for CMOS Image Sensor With Lateral Overflow Integration Capacitor │ Proceedings of 2022 International Workshop on Image Sensors and Systems │ (Poster-11) (共著)
9.	2022/03/01	Experimental Study of Fault Injection Attack on Image Sensor Interface for Triggering Backdoored DNN Models │ IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences │ E105-A (3) (共著)
10.	2022/02/28	Image Recognition of HDR Images Taken with Dual-Gain CIS │ Proceedings of the 2022 International Workshop on Nonlinear Circuits, Communication and Signal Processing │ ,2PM2-1-1 (共著)
11.	2021/11/15	Backdoor Attack on Deep Neural Networks Triggered by Fault Injection Attack on Image Sensor Interface │ Proceedings of the 5th Workshop on Attacks and Solutions in Hardware Security │ ,63-72頁 (共著)
12.	2021/09/10	Area-Efficient Post-Processing Circuits for Physically Unclonable Function with 2-Mpixel CMOS Image Sensor │ Sensors, MDPI AG │ 21 (18:6079) (共著)
13.	2021/03/08	Modeling attacks against device authentication using CMOS image sensor PUF │ IEICE Electronics Express │ 18 (7),20210058 (共著)
14.	2021/01/01	Model Reverse-Engineering Attack against Systolic-Array-Based DNN Accelerator Using Correlation Power Analysis │ IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences │ E104.A (1),152-161頁 (共著)
15.	2020/10/10	Model Reverse-Engineering Attack using Correlation Power Analysis against Systolic Array Based Neural Network Accelerator │ IEEE International Symposium on Circuits and Systems (ISCAS) │ ,1-5頁 (共著)
16.	2019	A 120-ke− Full-Well Capacity 160-µV/e− Conversion Gain 2.8-µm Backside-Illuminated Pixel with a Lateral Overflow Integration Capacitor │ Sensors, MDPI AG │ 19 (24:5572) (共著)
17.	2018	A Dynamic Soft-Decision Fuzzy Extractor for a CMOS Image Sensor PUF │ International Symposium on Intelligent Signal Processing and Communication Systems │ (共著)
18.	2018	An Over 90 dB Intra-Scene Single-Exposure Dynamic Range CMOS Image Sensor Using a 3.0 μm Triple-Gain Pixel Fabricated in a Standard BSI Process │ Sensors, MDPI AG │ 18 (1:203) (共著)
19.	2018	Single Exposure Type Wide Dynamic Range CMOS Image Sensor With Enhanced NIR Sensitivity │ Transactions on Media Technology and Applications,ITE │ 6 (3),195-201 (共著)
20.	2017	A Proposal of PUF Utilizing Pixel Variations in the CMOS Image Sensor │ Proceedings of International Image Sensor Workshop │ ,66-69 (共著)
21.	2017	An 87dB Single Exposure Dynamic Range CMOS Image Sensor with a 3.0um Triple Conversion Gain Pixel │ Proceedings of International Image Sensor Workshop │ ,274-277 (共著)
22.	2017	Backside Illuminated High Dynamic Range 3.0um Pixel Featuring Vertical p-n Junction Capacitance in a Deep Pinned Photodiode │ Proceedings of International Image Sensor Workshop │ ,169-172 (共著)
23.	2015	A 3.7 M-Pixel 1300-fps CMOS Image Sensor With 5.0 G-Pixel/s High-Speed Readout Circuit │ Journal of Solid-State Circuits, IEEE │ 48 (11),2608-2617 (共著)
24.	2014	A 3.7M-pixel 1300-fps CMOS image sensor with 5.0G-pixel/s high-speed readout circuit │ Symposium on VLSI Circuits Digest of Technical Papers │ ,1-2 (共著)
25.	2013	A low-power technique for pipelined ADCs with programmable gain amplification │ IEICE Electronics Express │ 10 (1),20120876 (共著)
26.	2013	Low-Power On-Chip Charge-Recycling DC-DC Conversion Circuit and System │ Journal of Solid-State Circuits, IEEE │ 48 (11),2608-2617 (共著)
27.	2012	Green semiconductor technology with ultra-low power on-chip charge-recycling power circuit and system │ IEEE Asian Solid State Circuits Conference │ ,105-108 (共著)
28.	2012	マージド・キャパシタ・スイッチング法を用いたパイプラインA-DコンバータのMDACセグメント内差動キャパシタミスマッチに関する解析 │ 電子情報通信学会論文誌C、電子情報通信学会 │ 95 (10),235-239 (共著)
29.	2012	入出力相互コンダクタンス及び位相補償容量を可変とする可変利得増幅器の低消費電力化に関する検討 │ 電子情報通信学会論文誌C、電子情報通信学会 │ 95 (7),131-138 (共著)
30.	2010	A Frequency Model of a Continuously Driven Clocked CMOS Comparator │ Transactions on Circuits and Systems II, IEEE │ 57 (12),956-960 (共著)
31.	2010	An Area-Efficient CMOS Bandgap Reference Utilizing a Switched-Current Technique │ Transactions on Circuits and Systems II, IEEE │ 57 (10),762-766 (共著)
32.	2009	A High Efficiency Variable Gain Amplifier Circuit with Controllable Transconductance Amp │ The transactions of the Institute of Electrical Engineers of Japan.C, IEEJ │ 129 (10),1968-1969 (共著)
33.	2009	A Reference Voltage Buffer with Settling Boost Technique for a 12bit 18MHz Multibit/Stage Pipelined A/D Converter │ TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, IEICE │ 92 (2),367-373 (共著)
34.	2007	A 10-bit 800-Column Low-Power RAM Bank Including Energy-Efficient D-Flip-Flops for a Column-Parallel ADC │ TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, IEICE │ 90 (2),358-364 (共著)
35.	2006	Frequency Response Analysis of Latch Utilized in High-Speed Comparator │ 13th IEEE International Conference on Electronics, Circuits and Systems │ ,1077-1080 (共著)