Researcher Database

OKURA SHUNSUKE

Department / Course College of Science and Engineering Department of Electronic and Computer Engineering

Title / Position Associate Professor

Papers
1.	2023/07/01	Image classification with SVM for CMOS sensor generating a vector image │ Journal of Signal Processing │ (Co-authored)
2.	2023/05/21	A Study on a Feature Extractable CMOS Image Sensor for Low-Power Image Classification System │ Proceedings of 2023 International Image Sensor Workshop │ (P33) (Co-authored)
3.	2023/05/21	A Study on Two Step Reset LOFIC Pixel to Reduce SNR Gap │ Proceedings of 2023 International Image Sensor Workshop │ (P10) (Co-authored)
4.	2023/05/14	Backdoor Attack on Deep Neural Networks Triggered by Fault Injection Attack on Image Sensor Interface │ Sensors, MDPI AG │ 23 (10:4742) (Co-authored)
5.	2023/05/04	An Area-Efficient up/down Double-Sampling Circuit for a LOFIC CMOS Image Sensor │ Sensors, MDPI AG │ 23 (9:4478) (Co-authored)
6.	2023/02/28	Image classification with SVM for CMOS sensor generating a vector image │ Proceedings of the 2023 International Workshop on Nonlinear Circuits, Communication and Signal Processing │ ,pp.1AM1-2-2 (Co-authored)
7.	2023/01/25	Fundamental Study of Adversarial Examples Created by Fault Injection Attack on Image Sensor Interface │ 2022 Asian Hardware Oriented Security and Trust Symposium (AsianHOST) │ (Co-authored)
8.	2022/12/12	A Variable-Resolution SAR ADC with 10-bit Image Capturing Mode and 5-bit Feature Extraction Mode │ Proceedings of 2022 International Workshop on Image Sensors and Systems │ (Poster-12) (Co-authored)
9.	2022/12/12	An area efficient readout circuit for CMOS Image Sensor With Lateral Overflow Integration Capacitor │ Proceedings of 2022 International Workshop on Image Sensors and Systems │ (Poster-11) (Co-authored)
10.	2022/03/01	Experimental Study of Fault Injection Attack on Image Sensor Interface for Triggering Backdoored DNN Models │ IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences │ E105-A (3) (Co-authored)
11.	2022/02/28	Image Recognition of HDR Images Taken with Dual-Gain CIS │ Proceedings of the 2022 International Workshop on Nonlinear Circuits, Communication and Signal Processing │ ,pp.2PM2-1-1 (Co-authored)
12.	2021/11/15	Backdoor Attack on Deep Neural Networks Triggered by Fault Injection Attack on Image Sensor Interface │ Proceedings of the 5th Workshop on Attacks and Solutions in Hardware Security │ ,pp.63-72 (Co-authored)
13.	2021/09/10	Area-Efficient Post-Processing Circuits for Physically Unclonable Function with 2-Mpixel CMOS Image Sensor │ Sensors, MDPI AG │ 21 (18:6079) (Co-authored)
14.	2021/03/08	Modeling attacks against device authentication using CMOS image sensor PUF │ IEICE Electronics Express │ 18 (7),pp.20210058 (Co-authored)
15.	2021/01/01	Model Reverse-Engineering Attack against Systolic-Array-Based DNN Accelerator Using Correlation Power Analysis │ IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences │ E104.A (1),pp.152-161 (Co-authored)
16.	2020/10/10	Model Reverse-Engineering Attack using Correlation Power Analysis against Systolic Array Based Neural Network Accelerator │ IEEE International Symposium on Circuits and Systems (ISCAS) │ ,pp.1-5 (Co-authored)
17.	2020/02/28	Dependency Evaluation between Performance Metrics and Response-Bit Length of a CIS-PUF │ Proceedings of the 2020 International Workshop on Nonlinear Circuits, Communication and Signal Processing │ ,pp.2AM2-3-3 (Co-authored)
18.	2019/06/23	A 2-Mpixel CMOS Image Sensor with Device Authentication and Encryption Key Generation based on Physically Unclonable Function │ Proceedings of 2019 International Image Sensor Workshop │ ,pp.119-122 (Co-authored)
19.	2019/06/23	A High Optical Performance 2.8µm BSI LOFIC Pixel with 120ke- FWC and 160µV/eConversion Gain │ Proceedings of 2019 International Image Sensor Workshop │ ,pp.246-249 (Co-authored)
20.	2019	A 120-ke− Full-Well Capacity 160-µV/e− Conversion Gain 2.8-µm Backside-Illuminated Pixel with a Lateral Overflow Integration Capacitor │ Sensors, MDPI AG │ 19 (24:5572) (Co-authored)
21.	2018	A Dynamic Soft-Decision Fuzzy Extractor for a CMOS Image Sensor PUF │ International Symposium on Intelligent Signal Processing and Communication Systems │ (Co-authored)
22.	2018	An Over 90 dB Intra-Scene Single-Exposure Dynamic Range CMOS Image Sensor Using a 3.0 μm Triple-Gain Pixel Fabricated in a Standard BSI Process │ Sensors, MDPI AG │ 18 (1:203) (Co-authored)
23.	2018	Single Exposure Type Wide Dynamic Range CMOS Image Sensor With Enhanced NIR Sensitivity │ Transactions on Media Technology and Applications,ITE │ 6 (3),pp.195-201 (Co-authored)
24.	2017	A Proposal of PUF Utilizing Pixel Variations in the CMOS Image Sensor │ Proceedings of International Image Sensor Workshop │ ,pp.66-69 (Co-authored)
25.	2017	An 87dB Single Exposure Dynamic Range CMOS Image Sensor with a 3.0um Triple Conversion Gain Pixel │ Proceedings of International Image Sensor Workshop │ ,pp.274-277 (Co-authored)
26.	2017	Backside Illuminated High Dynamic Range 3.0um Pixel Featuring Vertical p-n Junction Capacitance in a Deep Pinned Photodiode │ Proceedings of International Image Sensor Workshop │ ,pp.169-172 (Co-authored)
27.	2015	A 3.7 M-Pixel 1300-fps CMOS Image Sensor With 5.0 G-Pixel/s High-Speed Readout Circuit │ Journal of Solid-State Circuits, IEEE │ 48 (11),pp.2608-2617 (Co-authored)
28.	2014	A 3.7M-pixel 1300-fps CMOS image sensor with 5.0G-pixel/s high-speed readout circuit │ Symposium on VLSI Circuits Digest of Technical Papers │ ,pp.1-2 (Co-authored)
29.	2013	A low-power technique for pipelined ADCs with programmable gain amplification │ IEICE Electronics Express │ 10 (1),pp.20120876 (Co-authored)
30.	2013	Low-Power On-Chip Charge-Recycling DC-DC Conversion Circuit and System │ Journal of Solid-State Circuits, IEEE │ 48 (11),pp.2608-2617 (Co-authored)
31.	2012	Green semiconductor technology with ultra-low power on-chip charge-recycling power circuit and system │ IEEE Asian Solid State Circuits Conference │ ,pp.105-108 (Co-authored)
32.	2010	A Frequency Model of a Continuously Driven Clocked CMOS Comparator │ Transactions on Circuits and Systems II, IEEE │ 57 (12),pp.956-960 (Co-authored)
33.	2010	An Area-Efficient CMOS Bandgap Reference Utilizing a Switched-Current Technique │ Transactions on Circuits and Systems II, IEEE │ 57 (10),pp.762-766 (Co-authored)
34.	2009	A High Efficiency Variable Gain Amplifier Circuit with Controllable Transconductance Amp │ The transactions of the Institute of Electrical Engineers of Japan.C, IEEJ │ 129 (10),pp.1968-1969 (Co-authored)
35.	2009	A Reference Voltage Buffer with Settling Boost Technique for a 12bit 18MHz Multibit/Stage Pipelined A/D Converter │ TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, IEICE │ 92 (2),pp.367-373 (Co-authored)
36.	2007	A 10-bit 800-Column Low-Power RAM Bank Including Energy-Efficient D-Flip-Flops for a Column-Parallel ADC │ TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, IEICE │ 90 (2),pp.358-364 (Co-authored)
37.	2006	Frequency Response Analysis of Latch Utilized in High-Speed Comparator │ 13th IEEE International Conference on Electronics, Circuits and Systems │ ,pp.1077-1080 (Co-authored)